Semiconductor memory

A semiconductor integrated circuit device comprising:

• a plurality of memory arrays formed in a semiconductor chip, wherein each of said memory arrays includes a plurality of memory cells for holding data, said memory cells being spaced apart from one another by a predetermined distance;
• selecting means responsive to a predetermined address signal from said address forming means for selecting at least one memory cell from each of said memory arrays at a time, to form a predetermined set of data having check bits;
• and
• an error correcting code circuit formed in said semiconductor chip and coupled to receive said predetermined set of data from said memory arrays,
• wherein the selected memory cells are located to be spaced from one another by a distance greater than said predetermined distance.

A semiconductor integrated circuit device including a plurality of memory cells formed in one semiconductor chip, comprising:

• means for forming a predetermined address signal;
• selecting means, coupled to said forming means, for selecting a plurality of predetermined ones of said plurality of memory cells at a time in response to said predetermined address signal for reading out a predetermined set of data having check bits from said predetermined ones of said plurality of memory cells;
• an error correcting code circuit, formed in said semiconductor chip and coupled to said selecting means, for receiving said predetermined set of data having check bits from said selecting means;
• and
• output means, coupled to said error correcting code circuit, for outputting output data from said error correcting code circuit by dividing said output data into a predetermined bit number, in a time sharing manner,
• wherein said predetermined ones of the memory cells, for delivering said predetermined set of data having check bits, are located in said semiconductor chip so as to be spaced from each other by a distance of at least one of said memory cells.

A semiconductor integrated circuit device including a plurality of memory cells formed in one semiconductor chip, comprising:

• means for forming a predetermined address signal;
• selecting means, coupled to said forming means, for selecting a plurality of predetermined ones of said plurality of memory cells at a time in response to said predetermined address signal for reading out a predetermined set of data having check bits from said predetermined ones of said plurality of memory cells;
• an error correcting code circuit, formed in said semiconductor chip and coupled to said selecting means, for receiving said predetermined set of data having check bits from said selecting means;
• and
• output means, coupled to said error correcting code circuit, for outputting output data from said error correcting code, circuit by dividing said output data into a predetermined bit number, in a time sharing manner.