Demultiplexer for a serial and isochronous multiplex signal

Demultiplexer for a serial and isochronous multiplex signal consisting of Q (Q=2, 3, 4, . . . ) isochronous tributary signals interleaved block-by-block, each block comprising K (K=2, 3, 4, . . . ) bits, comprising:

• series to parallel converter means for converting W serial bits (W=1, 2, 3, . . . ) of the multiplex signal into W parallel bits, where W is a divisor of K;
• write/read memory means containing Q groups of memory locations each having K one-bit memory locations;
• write/read control means for simultaneously writing bits from the series to parallel converter into W consecutive memory locations of the write/read memory and reading out the bits from the K memory locations of one of groups cyclically and for commencing the reading process at the L.sup.th memory location of a group when the first memory location of the group is written into, where L=1+((K-Z) modulo K) and the integer Z fulfills the requirement 0.ltoreq.Z.ltoreq.(K-W)/Q, whereby, as a result of use of L for commencing reading, the writing process does not overtake the reading process;
• and
• means for combining the bits of the read memory locations of a group to form a serial tributary signal.