US 5,177,738 A · Process and a monolithically integrated device for speed adaptation for integrated services digital network (ISDN)

Abstract

The process of synchronization and decomposition of asynchronous frames organized with octet-rows of bits, for the adaptation of speed carried out by an intermediate reception block for adaptation of speed of an integrated device for the adaptation of synchronous and asynchronous terminals according to the CCITT V.110 standard to an Integrated Service Digital Network, is carried out by storing one octet at a time in an 8-bit shift register and by using counters in order to store the current position of each octet within a respective asynchronous frame and by recognizing by means of other counters and relevant bits of each octet, which are stored and switched to the respective elements for management and for control of the serial flow of data from the network to the terminal. From this, an architecture is derived, which is particularly simplified by means of the redimensioning of the registers which, instead of storing an entire frame, have to store only one octet at a time. Also, the delay undergone by the data in transfer by means of the block is reduced to the delay necessary for the shifting of a single octet. In fact, there will never be more than two octets at a time contained within the block instead of two frames or one, as would be necessary according to an architecture of conventional type. Two PLAs, each functioning with its own clock, manage and control the synchronization, the decomposition of the frames into octets and the addressing of the bits and, respectively, the flow of the data in input to an in output from the block in relation to said standard.

Claims13

Dependent claims

A process for synchronizing and decomposing asynchronous data frames of different length of a serial bit stream structured in octet-rows of bits containing frame synchronization bits and data bits, for rate adaptation of synchronous and asynchronous terminals of an Integrated Services Digital Network (ISDN) during data reception from the network comprising:

storing one octet at a time in a shift register;
identifying the current position of each octet shifting through said shift register within the respective asynchronous frame of said serial bit stream by first counter means;
identifying the octets forming a complete frame by second counter means;
loading the data bits contained in each identified octet of a frame in a parallel input data register;
and,
converting the data stored in said data register into an output serial bit stream of a rate lower than the rate of said incoming serial bit stream.

3 more elements

A data transfer apparatus for rate adaptation comprising:

a first shift register (RSC8) for receiving a synchronous serial bit stream of a certain rate, structured in octets grouped together in asynchronous frame of different length and containing data bits and frame synchronization bits;
a first counter (RSA) for identifying the presence of a valid octet in said first shift register (RSC8);
a second counter (RSB) for identifying the octets forming a complete frame;
a first input data controller state machine (RS2) for verifying said frame synchronization bits and loading into a second parallel input register (RSD) the data contained in each octet shifting through said first shift register (RSC8) and validly identified by means of said first counter (RSA) and said second counter (RSB);
a second output data controller state machine (RS9) for controlling the loading of data from said second register (RSD) to a third register (RSC6) in the form of a serial bit stream of a rate lower than the rate of said incoming serial stream.

2 more elements

Apparatus for rate adaptation of synchronous and asynchronous terminals of an Integrated Services Digital Network which comprises a reception block and a transmission block, wherein said reception block comprises:

a first shift register (RSC8) for receiving a synchronous serial bit stream of a certain rate, structured in octets grouped together in asynchronous frames of different length and containing data bits and frame synchronization bits;
a first counter (RSA) for identifying the presence of a valid octet in said first shift register (RSC8);
a second counter (RSB) for identifying the octets forming a complete frame;
a first input data controller state machine (RS2) for verifying said frame synchronization bits and determining the loading into a second parallel input register (RSD) of the data contained in each octet shifting through said first shift register (RSC8) and validly identified by means of said first counter (RSA) and said second counter (RSB);
and,
a second output data controller state machine (RS9) for controlling the loading of data from said second register (RSD) to a third register (RSC6) capable of delivering data in the form of a serial bit stream of a rate lower than the rate of said incoming serial stream.

3 more elements

Dependencies are inferred from the claim text.

Process and a monolithically integrated device for speed adaptation for integrated services digital network (ISDN)

Life of this patent

Process and a monolithically integrated device for speed adaptation for integrated services digital network (ISDN)

Life of this patent

Abstract

Claims13