Dynamic random access memory and method for equalizing sense amplifier drive signal lines

In a dynamic random access memory (DRAM) comprising a memory cell array, said memory cell array having rows and columns;

• a plurality of word lines for selecting one of said rows from said memory cell array;
• a plurality of bit lines for selecting one of said columns from said memory cell array, said bit lines having selected capacitances and formed in folded bit line pairs;
• equalizing transistors for each of said bit line pairs, said equalizing transistors activated in response to a first driving signal;
• a writing potential for writing a bit into a cell of said memory cell array being applied selectively to said bit lines for writing a bit into a corresponding cell of said array;
• first sense amplifiers formed of n channel MOS transistors provided for a respective one of said bit line pairs, said first sense amplifiers detecting and amplifying the difference of the bit line potentials of the bit line pair to which respective ones of said first sense amplifiers are connected, each said first sense amplifier activated in response to a second driving signal applied through a first signal line and generated at a timing after said first driving signal;
• second sense amplifiers formed of p channel MOS transistors provided for a respective one of said bit line pairs, said second sense amplifiers detecting and amplifying the difference of the bit line potentials of the bit line pair to which respective ones of said second sense amplifiers are connected, each said second sense amplifier activated in response to a third driving signal applied through a second signal line, said first and second signal lines having selected capacitances;
• a method of improving the operating margin of said sense amplifiers, comprising the steps of
• placing said first and second signal lines in a high impedance state, and
• in response to said first driving signal, connecting said driving signal lines of said sense amplifiers to each bit line of the bit line pairs so as to equalize the potential, due to said capacitances of said bit lines and said first and second signal lines, of each of said bit lines of said bit line pairs of said array at a common potential that is one half said writing potential of said array.

A dynamic random access memory comprising:

• a plurality of memory cells arranged in a matrix form of rows and columns;
• a plurality of word lines arranged in rows, each said word line connected to memory cells arranged in a respective row of said matrix;
• a plurality of bit line pairs arranged in columns and having selected capacitances, each said bit line pair connected to memory cells arranged in a respective column of said matrix;
• a plurality of equalizing transistors being made conductive at an equalizing period;
• each equalizing transistor connected between bit lines of a corresponding bit line pair;
• a plurality of first sense amplifiers, each said first sense amplifier having first and second n channel MOS transistors, said first n channel MOS transistor of each of said first sense amplifier connected between one bit line of a corresponding bit line pair and a first driving signal line having a selected capacitance, the gate electrode of said first n channel MOS transistor connected to the other bit line of said corresponding bit line pair;
• said second n channel MOS transistor of each said first sense amplifier connected between said other bit line and said first driving signal line;
• the gate electrode of said second n channel MOS transistor connected to said one bit line of said corresponding bit line pair;
• a plurality of second sense amplifiers, each said second sense amplifier having first and second p channel MOS transistors, said first p channel MOS transistor of each said second sense amplifier connected between said one bit line of a corresponding bit line pair and a second driving signal line having a selected capacitance, the gate electrode of said second p channel MOS transistor of each said second sense amplifier connected to said other bit line of said corresponding bit line pair, said second p channel transistor connected between said other bit line of said corresponding bit line pair and said second driving signal line, the gate electrode of said second p channel MOS transistor connected to said one bit line of said corresponding bit line pair;
• a plurality of first switching transistors being made conductive at said equalizing period;
• each first switching transistor connected between said one bit line of a corresponding bit line pair and said first driving signal line;
• a plurality of second switching transistors being made conductive at said equalizing period, each second switching transistor connected between the other bit line of a corresponding bit line pair and said first driving signal line;
• a plurality of third switching transistors being made conductive at said equalizing period, each third switching transistor connected between said one bit line of a corresponding bit line pair and said second driving signal line;
• and
• a plurality of fourth switching transistors being made conductive at said equalizing period, each fourth switching transistor connected between the other bit line of a corresponding bit line pair and said second driving signal line.