Memory with improved reading time
AssigneeSGS-Thomson Microelectronics S.A.
InventorFranck Edme
Life of this patent
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Abstract
To shorten the reading cycle of a memory, the memory cells of which comprise floating gate transistors, a circuit for pre-charging the bit lines of the memory is used, this circuit being independent of the reading sense amplifier proper. This pre-charging circuit includes a differential amplifier receiving, firstly, a voltage signal for the effective pre-charging of the bit line and, secondly, a pre-charging voltage reference signal. So long as the effective pre-charging has not reached the assigned value, the differential amplifier delivers a command signal to a power transistor that pre-charges the bit lines. As soon as the assigned pre-charging value is reached, the power transistor goes off, and the circuit of the amplifier is itself uncoupled.
Claims6
A memory comprising:
- a plurality of memory cells, each of which includes a floating gate transistor;
- bit lines to gain access to said memory cells;
- means for pre-charging said bit lines before a reading of memory cell electrical states;
- a differential amplifier receiving a pre-charging voltage reference signal to be compared with a voltage corresponding to an effective pre-charging of said bit lines, said differential amplifier delivering a charging command signal;
- said means for pre-charging said bit-lines comprising a power transistor activated by said command signal for pre-charging said bit lines;
- said power transistor having a drain, a source, and a gate, and being serially connected by its drain and source between a power supply and said bit lines, and receiving on its gate said command signal.
Dependencies are inferred from the claim text.