Semiconductor memory device having a plurality of ports

A semiconductor memory device of M words N bits having a plurality of ports, comprising:

• a memory cell array of a plurality of memory cells arranged in (M/n) rows and (n.times.N) columns, each including a data storage node;
• write word lines and read word lines commonly connected to memory cells of one row included in said memory cell array, respectively;
• n write column selecting lines provided corresponding to the number of words (n) included in one row of said memory cell array connected to every n (the number of words) memory cells of the memory cells of each of said rows;
• write bit lines and read bit lines connected to one column or plural of columns of memory cells included in said memory cell array;
• input terminals to which data is input for driving said write bit lines;
• and
• output terminals from which data read from said memory cells is output;
• wherein
• in response to data applied to any of said input terminals, said write bit lines are driven, and in response to a signal output to any of said write word lines and of said write column selecting lines, electrical connection between the write bit line and the data storage node of the memory cell connected to the write bit line is controlled, so that a first port is formed by the write bit lines, the write word lines and the input terminals;
• in order to drive any of said read bit lines to data corresponding to a value of the data storage node of said memory cell, the corresponding one of the read word lines is driven, and data corresponding to a signal on the read bit line is outputted to the corresponding one of said output terminals, so that a second port is formed by the read bit lines, the read word lines and the output terminals.