Division circuit using higher radices

A division circuit having a plurality of stages based on a repeat arithmetic operation method, each stage comprising:

• constant multiple means for multiplying a divisor by a predetermined constant multiple;
• first addition means for performing an addition operation between a dividend and a value obtained by multiplying the divisor by a constant multiple provided from the constant multiple means, and for outputting a sum component and a carry component as a result of the addition operation;
• shift means for shifting the sum component and the carry component by a shift amount in accordance with a radix;
• second addition means for performing an addition operation between the upper bits of the shifted sum component and the shifted carry component, obtained by the shift means, by predetermined bits;
• and
• third addition means for performing an addition operation between the upper bits of the result of the addition operation obtained by the second addition means in the preceding stage and the constant multiple value of the divisor obtained by the constant multiple means in the preceding stage;
• comparison means for outputting a part of a quotient comprising a plurality of bits by comparing the results obtained by the third addition means and the value obtained by multiplying the divisor by the constant multiple and for determining the value of the constant multiple of the constant multiple means based on the comparison result,
• wherein the value of the constant multiple at a following constant multiple means is determined by the output of the comparison means and the output of the second addition means, the sum component and the carry component obtained by the first addition means are provided to a first addition means in the following stage, and the dividend and zero in place of the sum component and the carry component are input to the first addition means in a first stage.