CMOS memory device with improved sense amplifier biasing
AssigneeOki Electric Industry Co., Ltd.
InventorsTamihiro Ishimura, Masahumi Miyawaki, Sanpei Miyamoto, Hidenori Uehara
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Abstract
A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.
Claims6
A semiconductor device comprising:
- a substrate having a major surface therein and having a first conductivity type;
- a first region, having a second conductivity type, formed in a first portion of the major surface and extending from the first portion into said substrate;
- second and third regions, each having the first conductivity type, respectively formed in second and third portions within the first portion and respectively extending from the second and third portions into said first region, said second and third regions defining a channel region therebetween;
- a gate electrode overlying the channel region;
- a second conductivity type of heavily doped region formed in a fourth portion within the first portion and extending from the fourth portion into said first region;
- and
- said third region being electrically connected to said heavily doped region.
A semiconductor device comprising:
- a substrate having a major surface therein and having a first conductivity type;
- a first region, having a second conductivity type, formed in a first portion of the major surface and extending from the first portion into said substrate;
- second and third regions, each having the first conductivity type, respectively formed in second and third portions within the first portion and respectively extending from the second and third portions into said first region, said second and third regions defining a first channel region therebetween;
- fourth and fifth regions, each having the first conductivity type, respectively formed in fourth and fifth portions within the first portion and respectively extending from the fourth and fifth portions into said first region, said fourth and fifth regions defining a second channel region therebetween;
- a first gate electrode overlying the first channel region;
- a second gate electrode overlying the second channel region;
- a second conductivity type of heavily doped region formed in a sixth portion within the first portion and extending from the sixth portion into said first region;
- and
- said third and fourth regions being electrically connected to said heavily doped region.
A semiconductor device comprising:
- a substrate having a major surface therein and having a first conductivity type;
- a first region, having a second conductivity type, formed in a first portion of the major surface and extending from the first portion into said substrate;
- second, third and fourth regions, each having the first conductivity type, respectively formed in second, third and fourth portions within the first portion and respectively extending from the second, third and fourth portions into said first region, said second and third regions defining a first channel region therebetween, said third and fourth regions defining a second channel region therebetween;
- a first gate electrode overlying the first channel region;
- a second gate electrode overlying the second channel region;
- and
- a second conductivity type of heavily doped region formed in a fifth portion within the first portion and extending from the fifth portion into said first region, said third region being electrically connected to said heavily doped region.
Dependencies are inferred from the claim text.