Semiconductor integrated circuit device

A semiconductor integrated circuit device comprising:

• a plurality of terminals including (i) first terminals used for both signal input and signal output and (ii) second terminals used only for signal input;
• a plurality of input/output buffer means each connected to a respective one of said first and second terminals, each of said input/output buffer means having substantially the same input capacitance,
• each of said plurality of input/output buffer means includes input buffer means and output buffer means;
• internal circuit means coupled to said plurality of input/output buffer means to carry out predetermined signal processing;
• output driver means for activating each output buffer means connected to said first terminal;
• and
• disabling means for disabling each output buffer means connected to said second terminal by applying a predetermined potential.

A semiconductor integrated circuit device comprising:

• a plurality of terminals including (i) first terminals used for both signal input and signal output and (ii) second terminals used only for signal input;
• a plurality of input/output buffer means each connected to a respective one of said first and second terminals, each of said input/output buffer means having substantially the same input capacitance,
• each of said plurality of input/output buffer means includes input buffer means and output buffer means, said input buffer means including circuit means for receiving data or an address signal and control signal applying means responsive to a predetermined activation signal to apply a control signal to said circuit means for passing said received data or address signal;
• and
• internal circuit means coupled to said plurality of input/output buffer means to carry out predetermined signal processing.

A semiconductor circuit device comprising:

• a plurality of terminals including (i) first terminals used for both signal input and signal output and (ii) second terminals used only for signal input;
• a plurality of input/output buffer means each connected to a respective one of said first and second terminals, each of said input/output buffer means having substantially the same input capacitance,
• each of said plurality of input/output buffer means includes input buffer means and output buffer means, said output buffer means including (i) a first transistor coupled between a predetermined first potential and a corresponding one of said plurality of terminals, and (ii) a second transistor coupled between a predetermined second potential and said corresponding terminal;
• and
• internal circuit means coupled to said plurality of input/output buffer means to carry out predetermined signal processing.

A semiconductor integrated circuit device comprising:

• a plurality of terminals comprising first terminals used for both signal input and signal output and second terminals used only for signal output,
• a plurality of input/output buffer means each connected to a respective one of said first and second terminals, each of said input/output buffer means having the same output capacitance,
• each of said plurality of input/output buffer means including input buffer means and output buffer means, and
• internal circuit means coupled to said plurality of input/output buffer means to carry out predetermined signal processing.

A semiconductor integrated circuit device comprising:

• a plurality of terminals including (i) first terminals used for both signal input and signal output and (ii) second terminals used only for signal output;
• a plurality of input/output buffer means each connected to a respective one of said first and second terminals, each of said input/output buffer means having substantially the same output capacitance,
• each of said plurality of input/output buffer means includes input buffer means and output buffer means;
• internal circuit means coupled to said plurality of input/output buffer means to carry out predetermined signal processing;
• and
• output driver means for activating each output buffer means.

A semiconductor integrated circuit device comprising:

• a plurality of terminals including (i) first terminals used for both signal input and signal output and (ii) second terminals used only for signal output;
• a plurality of input/output buffer means each connected to a respective one of said first and second terminals, each of said input/output buffer means having substantially the same output capacitance,
• each of said plurality of input/output buffer means includes input buffer means and output buffer means, and
• internal circuit means coupled to said plurality of input/output buffer means to carry out predetermined signal processing, wherein
• said input buffer means connected to said first terminal comprises first circuit means for receiving data or an address signal and first control signal applying means responsive to a predetermined activation signal to apply a control signal to said first circuit means for passing said received data or address signal, and
• said input buffer means connected to said second terminal comprises second circuit means having substantially the same structure as said first circuit means and second control signal applying means having substantially the same structure as said first control signal applying means and receiving a predetermined potential in place of said activation signal.

A semiconductor integrated circuit device comprising:

• a semiconductor chip,
• a plurality of memory cells formed on said semiconductor chip,
• a plurality of terminals formed on said semiconductor chip and receiving data and address signals,
• a plurality of input/output buffer means connected to said plurality of terminals, respectively, and having the same input/output capacitance,
• each of said plurality of input/output buffer means including input buffer means and output buffer means,
• first processing means formed on said semiconductor chip and coupled to predetermined input/output buffer means of said plurality of input/output buffer means,
• said first processing means having a first number of address input portions receiving the address signals through some of said plurality of terminals and the corresponding input/output buffer means, and a second number of data receiving portions receiving the data and being responsive to the address signals applied to said address input portions for selecting said second number of memory cells, out of said plurality of memory cells and writing the data applied to said data receiving portion to the selected memory cells or reading out the data stored in the selected memory cells to said data receiving portions,
• second processing means formed on said semiconductor chip and coupled to predetermined input/output buffer means of said plurality of input/output buffer means,
• said second processing means having a third number of address input portions receiving the address signals through some of said plurality of terminals and the corresponding input/output buffer means, and a fourth number of data receiving portions receiving the data and being responsive to the address signals applied to said address input portions for selecting said fourth number of memory cells, out of said plurality of memory cells and writing the data applied to said receiving portions to the selected memory cells or reading out the data stored in the selected memory cells to said data receiving portions,
• switching signal generating means formed on said semiconductor chip for generating a switching signal, and
• signal switching means formed on said semiconductor chip and responsive to a first state of said switching signal generated by said switching signal generating means for coupling said address input portions and said data receiving portions in said first processing means to predetermined terminals, out of said plurality of terminals, through the corresponding input/output buffer means and responsive to a second state of said switching signal generated by said switching signal generating means for coupling said address input portions and said data receiving portion in said second processing means to a predetermined terminal, out of said plurality of terminals through the corresponding input/output buffer means.

On a single chip, a semiconductor integrated circuit device for a random access memory operable in two or more alternative configurations, comprising:

• a plurality of memory cells;
• a predetermined number of input/output terminals, said input/output terminals comprising a first set of terminals having set of terminals having the same function for each of said configurations and second set of terminals having different functions in different configurations;
• a plurality of buffer circuits, each comprising an input buffer circuit portion and an output buffer circuit portion connected to one of said input/output terminals, the input/output capacitance of all of said buffer circuits being the same;
• conditioning means responsive to an external signal, indicative of a selected configuration, for conditioning said plurality of buffer circuits for operation in accordance with the functions of said input/output terminals in the selected configuration.

A semiconductor integrated circuit device comprising:

• and output terminal for receiving an input signal and outputting an output signal;
• an input terminal for receiving an input signal;
• a first buffer circuit comprising first and second circuits, an input node of said first circuit connected to said input and output terminal, an output node of said first circuit connected to an input node of an internal circuit, an input node of said second circuit connected to an output node of said internal circuit, an output node of said second circuit connected to said input and output terminal;
• and
• a second buffer circuit comprising third and fourth circuits, the structure of said third circuit being the same as the structure of said first circuit, the structure of said fourth circuit being the same as the structure of said second circuit, an input node of said third circuit connected to said input terminal, an output node of said third circuit connected to an input node of said internal circuit, and an output node of said fourth circuit connected to said input terminal.

A semiconductor integrated circuit device comprising:

• an input and output terminal for receiving an input signal and outputting an output signal;
• an output terminal for outputting an output signal;
• a first buffer circuit comprising first and second circuits, an input node of said first circuit connected to said input and output terminal, an output node of said first circuit connected to an input node of an internal circuit, an input node of said second circuit connected to an output node of said internal circuit, an output node of said second circuit connected to said input and output terminal;
• and
• a second buffer circuit comprising third and fourth circuits, the structure of said third circuit being the same as the structure of said first circuit, the structure of said fourth circuit being the same as the structure of said second circuit, an input node of said third circuit connected to said output terminal, an input node of said fourth circuit connected to an output node of said internal circuit, and an output node of said fourth circuit connected to said output terminal.

A semiconductor integrated circuit device comprising:

• a plurality of terminals including (i) first bonding pads used for both signal input and signal output and (ii) second bonded pads used only for signal input;
• a plurality of input/output buffer means each permanently connected to a respective one of said first and second bonding pads, each of said input/output buffer means having substantially the same input capacitance,
• each of said plurality of input/output buffer means includes input buffer means and output buffer means, and
• internal circuit means coupled to said plurality of input/output buffer means for performing predetermined signal processing.

A semiconductor integrated circuit device comprising:

• a plurality of terminals including (i) first bonding pads used for both signal input and signal output and (ii) second bonded pads used only for signal output;
• a plurality of input/output buffer means each permanently connected to a respective one of said first and second bonding pads, each of said input/output buffer means having substantially the same output capacitance,
• each of said plurality of input/output buffer means includes input buffer means and output buffer means, and
• internal circuit means coupled to said plurality of input/output buffer means for performing predetermined signal processing.