US 5,177,484 AGranted

Switched capacitor oversampling analog/digital converter with noise filtering

AssigneeSiemens Aktiengesellschaft

InventorDieter Bruckmann

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Abstract

An oversampling analog/digital converter includes a given number of at least three identically constructed switched-capacitor converter stages each being triggered by an analog input signal and each outputting both an analog and a digital output signal. The converter stages are connected in series with respect to the analog input and output signals. The given number of series-connected differentiation stages are each connected downstream of a respective one of the converter stages for receiving and adding the digital output signals of the converter stages.

Claims6

Dependent claims

An oversampling analog/digital converter, comprising a given number of at least three identically constructed converter stages each being triggered by an analog input signal and each outputting both an analog and a digital output signal;

said converter stages being connected in series with respect to the analog input and output signals and forming a given number of series-connected differentiation stages;
said given number of series-connected differentiation stages each being connected downstream of a respective one of said converter stages for receiving and adding the digital output signals of said converter stages;
each of the converter stages having an operational amplifier with inverting and non-inverting inputs and with an output supplying the analog output signal of said respective converter stage, a comparator connected downstream of said operational amplifier, and a storage element connected downstream of said comparator, said storage element having one output supplying the digital output signal of said respective converter stage and another output supplying an inverted digital output signal;
each of said converter stages having first through fourteenth controllable switches and first through fifth capacitors each with two terminals;
in each of said converter stages said first switch receiving the respective analog signal and being connected to one of the terminals of said first capacitor, the second and third switches receiving a first reference potential and being connected in series to the one terminal of said first capacitor, said fourth switch receiving the respective analog signal and being connected to one of the terminals of said second capacitor, said fifth and sixth switch receiving a second reference potential and being mutually connected in series and to the one terminal of said second capacitor;
in each of the converter stages said seventh switch receiving a third reference potential and being connected to the other of the terminals of said first capacitor, said eighth switch being connected to the other terminal of said first capacitor, said ninth switch receiving the third reference potential and being connected to said eighth switch, one of the terminals of said third capacitor being connected to said eighth switch, the other of the terminals of said third capacitor being connected to the inverting input of said operational amplifier;
in each of said converter stages said tenth switch receiving the third reference potential and being connected to the other of the terminals of said second capacitor, and said eleventh switch being connected between the other terminal of said second capacitor and the inverting input of said operational amplifier;
in each of said converter stages the twelfth switch and said fourth capacitor being connected in series between the output of said operational amplifier and the one terminal of said third capacitor, said fifth capacitor being connected to the output of said operational amplifier, said thirteenth switch receiving the third reference potential and being connected to said fifth capacitor, and said fourteenth switch being connected between said fifth capacitor and the inverting input of said operational amplifier;
in each of said converter stages said first and fourth switches being controlled by a first clock signal;
said sixth, ninth, eleventh and fourteenth switches being controlled by a second clock signal;
said third and eighth switches being controlled by a third clock signal;
said seventh switch being controlled by a fourth clock signal;
said tenth, twelfth and thirteenth switches being controlled by a fifth clock signal;
said fifth switch being controlled by the inverted digital output signal and said second switch being controlled by the digital output signal;
and
the first, second and third clock signals being successively occurring, cyclically recurring pulses effecting switching of said respectively assigned switches, and the fourth and fifth clock signals being pulses effecting switching of said respectively assigned switches, the fourth clock signal beginning with a pulse of the first clock signal and ending with a pulse of the second clock signal, and the fifth clock signal beginning with a pulse of the third clock signal and ending with a pulse of the first clock signal.

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Dependencies are inferred from the claim text.

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Abstract

said converter stages being connected in series with respect to the analog input and output signals and forming a given number of series-connected differentiation stages;
said given number of series-connected differentiation stages each being connected downstream of a respective one of said converter stages for receiving and adding the digital output signals of said converter stages;
each of the converter stages having an operational amplifier with inverting and non-inverting inputs and with an output supplying the analog output signal of said respective converter stage, a comparator connected downstream of said operational amplifier, and a storage element connected downstream of said comparator, said storage element having one output supplying the digital output signal of said respective converter stage and another output supplying an inverted digital output signal;
each of said converter stages having first through fourteenth controllable switches and first through fifth capacitors each with two terminals;
in each of said converter stages said first switch receiving the respective analog signal and being connected to one of the terminals of said first capacitor, the second and third switches receiving a first reference potential and being connected in series to the one terminal of said first capacitor, said fourth switch receiving the respective analog signal and being connected to one of the terminals of said second capacitor, said fifth and sixth switch receiving a second reference potential and being mutually connected in series and to the one terminal of said second capacitor;
in each of the converter stages said seventh switch receiving a third reference potential and being connected to the other of the terminals of said first capacitor, said eighth switch being connected to the other terminal of said first capacitor, said ninth switch receiving the third reference potential and being connected to said eighth switch, one of the terminals of said third capacitor being connected to said eighth switch, the other of the terminals of said third capacitor being connected to the inverting input of said operational amplifier;
in each of said converter stages said tenth switch receiving the third reference potential and being connected to the other of the terminals of said second capacitor, and said eleventh switch being connected between the other terminal of said second capacitor and the inverting input of said operational amplifier;
in each of said converter stages the twelfth switch and said fourth capacitor being connected in series between the output of said operational amplifier and the one terminal of said third capacitor, said fifth capacitor being connected to the output of said operational amplifier, said thirteenth switch receiving the third reference potential and being connected to said fifth capacitor, and said fourteenth switch being connected between said fifth capacitor and the inverting input of said operational amplifier;
in each of said converter stages said first and fourth switches being controlled by a first clock signal;
said sixth, ninth, eleventh and fourteenth switches being controlled by a second clock signal;
said third and eighth switches being controlled by a third clock signal;
said seventh switch being controlled by a fourth clock signal;
said tenth, twelfth and thirteenth switches being controlled by a fifth clock signal;
said fifth switch being controlled by the inverted digital output signal and said second switch being controlled by the digital output signal;
and
the first, second and third clock signals being successively occurring, cyclically recurring pulses effecting switching of said respectively assigned switches, and the fourth and fifth clock signals being pulses effecting switching of said respectively assigned switches, the fourth clock signal beginning with a pulse of the first clock signal and ending with a pulse of the second clock signal, and the fifth clock signal beginning with a pulse of the third clock signal and ending with a pulse of the first clock signal.

13 more elements