Multilevel configurable logic analyzer

Abstract

A logic analyzer is provided with probes (20) deriving the signals to be tested which are introduced into a digitizer (22) provided with comparators which carry out a digitization according to a logic system having two states. It comprises a change-over circuit (21) arranged between the probe and the digitizer, which permits associating several or all comparators with a given signal to be tested to extend its digitization to a multi-level logic system. The change-over circuit (21) is constituted by a matrix of MOS transfer gates or field effect transistors (FET's). When the multi-level logic system has at least one medium state limited by two references, the medium state is displayed on a display device (24) according to a straight line or a monotonic curve joining the two references between the beginning and the end of the medium state. When the duration of the medium state exceeds a predetermined duration, the display device (24) is switched on to display the medium state.

Dependencies are inferred from the claim text.