RLL encoder and decoder with pipelined plural byte processing
AssigneeInternational Business Machines Corporation
InventorsRoy D. Cideciyan, Erwin A. Zurfluh
Life of this patent
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Abstract
For encoding a stream of k-bit data bytes into a stream of m-bit code bytes satisfying given constraints, a coding principle and coder apparatus are disclosed which allow pipelined and parallel handling of the byte stream. Each data byte DB and an associated coder state indicator S are together converted into a code byte CB. The coder state indicator S(i) to be associated with a data byte DB(i) is obtained by logically combining the coder state indicator S(i-1) of the preceding data byte DB(i-1) and a state transition indicator T(i-1) derived from the latter. This allows the simultaneous generation of all coder state indicators S for a whole group (a word) of data bytes, thereby enabling the parallel and pipelined operation of the coder.
Claims17
Method for encoding sequential k-bit data bytes into sequential m-bit code bytes satisfying predetermined constraints, where k<m, using a coding procedure having at least two states,
- the method comprising the following steps:
- generating a state transition indicator T(i-1) for the encoding of each data byte DB(i), in dependence of the bit values of the respective preceding data byte DB(i-1);
- and
- encoding q data bytes DB(N) . . . DB(N+q-1) in parallel by
- generating simultaneously a coder state indicator S(i) for each data byte DB(i) of a set of q data bytes, by logically combining the coder state indicator S(i-1) associated with the respective preceding data byte DB(i-1) and the state transition indicator T(i-1) generated in dependence of the respective preceding data byte DB(i-1), and
- converting each data byte DB(i) of the set of q data bytes together with the associated coder state indicator S(i) into an assigned m-bit code byte CB(i).
Coder for generating code bytes, comprising q parallel sections and at least two pipeline stages,
- each of said parallel sections being provided for converting an input data byte DB(i) into an output code byte CB(i), and including
- in a first pipeline stage (40), a register (11) for a data byte DB(i) and the associated coder state indicator S(i), and means (32) for generating a new coder state indicator;
- and
- in a second pipeline stage, code conversion means (19) receiving as inputs (13;
- 15) a data byte DB(i) and the associated coder state indicator S(i), and furnishing at its output (21) the respective code byte CB(i);
- interconnection means (30;
- 36) being provided between the first pipeline stages of neighbor sections for transferring a coder state indicator from one section to the next.
Dependencies are inferred from the claim text.