Source-coupled FET logic circuit
AssigneeKabushiki Kaisha Toshiba
InventorHironori Nagasawa
Life of this patent
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Abstract
A source-coupled FET logic (SCFL) circuit having a switching section and a source-follower section. The switching section receives two input signals, and out puts two signals, which are at complementary levels, to the source-follower section. The source-follower section comprises two FETs, two level-shifting circuits, a current source, and two capacitors. The first and second FETs receive at their gates the two signals output by the switching section, respectively. The first and second level-shifting circuits are connected to the sources of the first and second FETs, respectively. Either level-shifting circuit comprises n diodes connected in series. The two capacitors are connected in parallel to the first and second level-shifting circuits, respectively.
Claims1
A source-coupled FET logic circuit comprising:
- a first node to which a higher voltage power supply is applied;
- a second node to which a lower voltage power supply is applied;
- a first FET and a second FET, each having a source, a drain, and a gate, the sources of said first and second FET being connected together, thus forming a source node;
- a first load element connected between said first node and the drain of said first FET;
- a second load element connected between said second node and the drain of said second FET;
- a first constant current source connected between said second node and said source node;
- a third FET having a source, a drain connected to said first node, and a gate connected to the drain of said first FET;
- a first level-shifting circuit comprising a plurality of level-shifting elements connected in series each having a first end and a second end, said first end being connected to the source of said third FET;
- a second constant current source connected between said second node and the second end of said first level-shifting circuit;
- a first capacitance circuit comprising a plurality of capacitors connected in parallel to the level-shifting elements of said first level-shifting circuit, respectively;
- a fourth FET having a source, a drain connected to said first node, and a gate connected to the drain of said second FET;
- a second level-shifting circuit comprising a plurality of level-shifting elements connected in series each having a first end and a second end, said first end being connected to the source of said fourth FET;
- a third constant current source connected between said second node and the second end of said second level-shifting circuit;
- and
- a second capacitance circuit comprising a plurality of capacitors connected in parallel to the level-shifting elements of said second level-shifting circuit, respectively.
Dependencies are inferred from the claim text.