Power on reset circuit for semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device comprising an internal reset circuit generating one shot pulse for resetting an internal circuit upon a power on. In the internal reset circuit, inputted to a two-input NOR gate are an output potential of an inverter inverting a first node coupled to a power supply through a capacitor, and an internal clock signal which level inverts at a predetermined timing after rising to a "H" level upon the power on. Then, the output of the NOR gate is applied to a second node in an internal circuit to be reset. The internal reset circuit outputs one shot pulses synchronizing with the first fall of the internal clock signal after the power on irrespective of a potential change rate of the first node after the power on. The first node is set to more easily attain a "H" level than the second node to be reset to a "L" level at the power on by adjusting characteristics of circuit elements connected to the first node and those of circuit elements connected to the second node. As a result, the second node is set to be without fail at a "L" level requiring no resetting when the inverted potential of the first node has a value allowing a generation of one shot pulses at the NOR gate, thereby preventing malfunction of the internal circuit due to erroneous resetting.

Dependencies are inferred from the claim text.