Pulse width modulation signal generating circuit providing N-bit resolution

A digital circuit for providing an N-bit resolution even when N-bit digital data is decreased to N-n bit digital data (N and n are positive integers and N>n), said digital circuit comprising:

• means for latching N-bit digital data for a predetermined period of time;
• means for cyclically counting N-bit binary data;
• a first adding circuit connected to means for latching and means for cyclically counting for adding n least significant bits of the N-bit digital data and n most significant bits of the N-bit binary data and for generating first pulse width modulation data;
• and
• a second adding circuit for adding N-n most significant bits of the N-bit digital data and N-n least significant bits of the N-bit binary data and for generating second pulse width modulation data;
• wherein said second adding circuit is capable of, in accordance with said first pulse width modulation data, adding on a time-divisional basis pulse width modulation data corresponding to a signal having a pulse width of T/2.sup.(N-n) (T is a time period of one cycle) to said second pulse width modulation data which are generated by said second adding circuit.