Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path

Abstract

A process for fabricating, on the more or less vertical edge of a silicon mesa, a MOS field-effect transistor which has a spacer-shaped gate and a right-angled channel path. The process involves the following steps: creating a raised region (the mesa) on a planar silicon substrate; creation of a gate oxide layer on the substrate and vertical sidewalls of the mesa; blanket deposition of a gate layer (typically polysilicon); anisotropically etching the gate layer to expose the upper surface of the mesa and leave a stringer gate around the circumference thereof; and doping the upper surface of the mesa and regions of the substrate peripheral to the circumferential polysilicon stringer to create source and drain regions. The standard process provides device density approximately double that of standard FET fabrication processes. Density can be increased even further by increasing the number of silicon mesas with a minimum pitch distance. This may be accomplished by employing the reduced-pitch masking technique disclosed in a copending U.S. patent application. Multiple transistors may be created on a single mesa by creating isolation regions within the mesa. The circumferential gate may be severed so as to provide a pair of gate inputs for transistors created on a single mesa. Enhancements common to conventional MOSFETS, such as lightly-doped source and drains, halos, etc., may be utilized for the new MOSFET process.

Dependencies are inferred from the claim text.