Central processing unit in a computer system for controlling a manufacturing line

A computer system comprising

• main processor means (102) for providing a read signal, an address strobe signal, a data strobe signal, and a write signal;
• a first bus (B1) connected to said main processor means and having capacity to transmit a predetermined number of bits per unit time;
• a main memory (MM) connected to said first bus and accessed by said main processor means;
• DMA controller means (104) connected to said first bus for executing direct memory access to said main memory;
• one or more input-output boards (C1 . . . CN);
• VME bus controller means (105) connected to said first bus (B1) for controlling said one or more input-output boards (C1 . . . CN);
• a second bus (B4) having capacity to transmit a smaller number of bits per unit time than said predetermined number of bits per unit time of said first bus;
• CRT displaying controller means (117,116,118) connected to said second bus (B4) and comprising a CRT display apparatus (CRT), a graphic display controller (116) to control graphic display on said CRt display apparatus, and character display controller means (118) to control character display on said CRT display apparatus;
• communication processing means (115) connected to said second bus (B4) for processing signals to and from said computer system;
• a third bus (B3) having a capacity to transmit a smaller number of bits per unit time than said predetermined number of bits per unit time of said first bus;
• slave processor means (110) connected to said third bus for controlling components connected to said third bus and for controlling other functions as desired;
• calender clock means (112) for providing clock signals to said slave processor means;
• peripheral device control means (111) connected to said third bus (B3) for controlling one or more peripheral devices;
• peripheral controller means (106) connected between said first bus (B1) and said third bus (B3) for controlling the timing of signals from said main processor means and said slave processor means and directed to control said one or more peripheral devices;
• and
• control means (101 and 5 of FIG. 3) connected between said first bus (B1) and said second bus (B4) for converting the number of bits per unit time of signals carried on said first bus (b1) to the number of bits per unit time of signals carried on said second bus (B4) said control means (101,5) comprising a buffer means (5b) and a control circuit means (5c);
• wherein
• said buffer means (5b) provides data to said first bus (B1) and to said second bus (B4);
• and wherein
• said control circuit means (5c) causes delay of said address strobe signal and said data strobe signal from said main processor means (102) when said read signal is provided by said main processor means (102);
• said control circuit means (5c) causes storing of said read signal in said buffer means (5b) and generating of a timing signal to trigger transmitting of the store read signal to said first bus (B1);
• said control circuit means (5c) causes delay of said address strobe signal and said data strobe signal from said main processor means (102) when said write signal is provided by said main processor means (102),
• said control circuit means (5c) causes storing of said write signal in said buffer means (5b) and generating of a timing signal to trigger transmitting of said stored write signal to said second bus (B4), and thereafter generating a chip select signal, and
• said control circuit means (5c) causes transmission of said chip select signal to said one or more input-output boards to prohibit transmission of signals before said address strobe signal and said data strobe signal are negated, whereby data are transferred at high speed in succeeding cycles without overlapping.