US 5,175,703 AGranted

High speed full adder and method

AssigneeMotorola, Inc.

InventorRichard H. Ong

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Abstract

A high-speed current mode 2-bit full adder using ripple carry with two full adders using three-levels of series gating, a bandgap reference voltage generator, two sum out buffers, and a carry out buffer. The method for the addition of an input carry bit and two 2-bit input bytes uses a logic circuit satisfying Boolean expressions SUM=ABC+AB'C'+A'B'C+A'BC' and C.sub.OUT =BC+AC+AB, where first 2-bit input byte A.sub.1 B.sub.1 and carry in byte C.sub.IN produce SUM equal to first bit sum S.sub.1 and an intermediate carry out bit at two voltage levels, C.sub.2, and C.sub.3 to facilitate processing. Second 2-bit byte A.sub.2 B.sub.2 and an intermediate carry out bit at C.sub.2 and C.sub.3, input to the bit 2 full adder, produce SUM equal to secondd bit sum S.sub.2 and final carry out bit C.sub.OUT. Each sum function uses only one current source to reduce components, lower power consumption, and improve efficiency.

Claims18

Dependent claims

A high-speed current mode logic 2-bit full adder with three level voltage logic and series gating comprising:

first full adder means for receiving inputs A.sub.1, B.sub.1, and carry in bit C.sub.IN and for producing a first-level output byte Z.sub.1 in accordance with the Boolean logic expression Z.sub.1 =A.sub.1 B.sub.1 C.sub.IN +A.sub.1 B.sub.1 'C.sub.IN '+A.sub.1 'B.sub.1 'C.sub.IN +A.sub.1 'B.sub.1 C.sub.IN ';
second full adder means coupled to the first full adder means, the second full adder means for receiving inputs A.sub.2, B.sub.2, C.sub.2, and C.sub.3 and for producing a second output Z.sub.2 in accordance with the Boolean logic expression:
Z.sub.2 =A.sub.2 B.sub.2 C+A.sub.2 B.sub.2 'C'+A.sub.2 'B.sub.2 'C+A.sub.2 'B.sub.2 C', where C=C.sub.2 at a second voltage level and C=C.sub.3 at a third voltage level;
bandgap reference voltage generator means to supply a plurality of supply voltages coupled to the first full adder means via a first plurality of connections and to the second full adder means via a second plurality of connections;
first sum out buffer means coupled to the first full adder means and to the bandgap reference voltage generator means via a third plurality of connections;
second sum out buffer means coupled to the second full adder means and to the bandgap reference voltage generator means via a fourth plurality of connections;
and
carry out buffer means coupled to the second full adder means and to the bandgap reference voltage generator means via a fifth plurality of connections.

5 more elements

A soft-saturation current mode arithmetic logic unit, using voltages V.sub.CC, V.sub.CS, V.sub.EE, and V.sub.REF, operating on inputs A, B and C to produce a sum bit, S, and a carry out bit, C.sub.OUT, in accordance with the Boolean logic expressions:

S=ABC+AB'C'+A'B'C+A'BC' and C.sub.OUT =BC+AC+AB, where X'=NOT X, the arithmetic logic unit comprising:
sum logic means comprising a first sum operator, a second sum operator coupled to the first sum operator, and a third sum operator coupled to the second sum operator, the sum logic means to produce a sum bit;
and
carry logic means comprising a first carry operator coupled to the first sum operator, a second carry operator coupled to the first carry operator and to the second sum operator, and a third carry operator coupled to the third sum operator and to the second carry operator, the carry logic means to produce C.sub.OUT at two output levels, C.sub.2 and C.sub.3.

1 more element

Dependencies are inferred from the claim text.