Phase-locked loop synthesizer for use in TDM communications system
AssigneeNEC Corporation
InventorRyuhei Fujiwara
Life of this patent
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Abstract
An analog switch is provided in a phase-locked loop (PLL) synthesizer using direct digital synthesizer (DDS) circuitry, for opening a PLL. The PLL is closed to make operative the DDS circuitry and a fixed frequency divider within an idle time slot of each time-division multiplexing (TDM) frame. For the rest of the frame, the voltage-controlled oscillator within the PLL is held in a "hold state".
Claims12
A phase-locked loop (PLL) synthesizer for generating a carrier wave for use with a radio communications unit utilizing time division multiplexing of at least a data transmission time slot and an idle time slot in each data transfer frame, comprising:
- direct digital synthesizer (DDS) circuitry for generating a reference frequency signal;
- a fixed frequency divider for dividing the frequency of the synthesizer output signal of said PLL synthesizer by a predetermined frequency division ratio;
- a phase comparator for comparing the phases of said reference frequency signal and the output signal of said fixed frequency divider;
- a loop filter circuit for smoothing the output signal of said phase comparator;
- an analog switch provided between said phase comparator and said loop filter circuit;
- and
- a voltage-controlled oscillator (VCO) for varying the frequency of said synthesizer output signal in response to the output signal of said loop filter circuit,
- said analog switch being held in an ON state during a predetermined period of time in said idle time slot and said DDS circuitry and said fixed frequency divider being enabled during said predetermined period of time.
A phase-locked loop (PLL) synthesizer for use in a time-division multiplexing (TDM) communications system using TDM frames each of which includes at least an idle time slot, said synthesizer comprising:
- direct digital synthesizer (DDS) means for generating a reference frequency signal, said DDS means being enabled in response to a control signal;
- voltage-controlled oscillator (VCO) means for generating an oscillation signal in accordance with a control voltage;
- phase comparator means for phase comparing said reference frequency and oscillation signals to produce a phase error signal representative of a phase difference therebetween;
- filter means for filtering said phase error signal to produce a filtered voltage and supplying said filtered voltage to said VCO means as said control voltage;
- and
- switching means connected between said phase comparator and filter means for selectively passing said phase error signal to said filter means in response to said control signal, said control signal being applied to said DDS and switching means for a predetermined period of time within said idle time slot.
A method of reducing power consumption on a phase-locked loop (PLL) synthesizer including direct digital synthesizer (DDS) circuitry, comprising the steps of:
- generating an oscillation signal in accordance with a control voltage;
- comparing the phases of said oscillation signal and the output of said DDS circuitry to produce an error signal;
- filtering said phase error signal to produce and apply a filtered voltage to said generating step as said control voltage;
- disabling said DDS circuitry for a predetermined period of time within an idle time slot of a time-division multiplexing (TDM) frame;
- and
- inhibiting said phase error signal from reaching said filtering step for said predetermined period of time.
Dependencies are inferred from the claim text.