Method of and device for demodulating biphase modulated signal
AssigneeSGS-Thomson Microelectronics S.A.
InventorGerhard Roither
Life of this patent
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Abstract
A method of demodulating a biphase modulated signal is implemented by first establishing a reference phase angle level. The biphase modulated signal contains a series of bits, each bit having first and second half-bits. The half-bits are represented by opposite phase angle levels. First and second phase angle levels correspond to the first and second half-bits respectively. After the levels associated with first and second half-bits are measured, the two levels are compared. A binary value is assigned to each pair of first and second half-bits based on the relationship of their respective levels. For example, a high phase angle level followed by a low level, can represent the binary value "1", and vice versa.
Claims12
A method of demodulating a biphase modulated signal comprising:
- measuring a first phase angle variation of said biphase modulated signal corresponding to a first half-bit of said biphase modulated signal,
- measuring a second phase angle variation of said biphase modulated signal corresponding to a second half-bit of said biphase modulated signal,
- comparing said first and second phase angle variations of said biphase modulated signal, and
- assigning a binary value to each pair of said first and second half-bits based on a relationship between said first and second phase angle variations.
A device for demodulating a signal that is biphase modulated with a binary bit sequence, in which each binary bit comprises a first half-bit and a second half-bit and a change in binary value is represented by a phase shift of a carrier wave, as a part of a digital system, comprising:
- an up/down counter which has a counting pulse input, an up/down switching control input, a resetting input and a counter output,
- an AND circuit having an output coupled to said counting pulse input and including a counting clock input, a signal input and a time window input,
- an assessment means coupled to the counter output for evaluating the count of the counter present at the bit end and, depending on the sign of this count, outputting the binary value "1" or the binary value "0", with these binary values determining the demodulated bit sequence,
- the up/down switching control input being fed with a signal corresponding to the bit sequence in frequency position and phase position, such that up counting is controlled during the one half-bit and down counting is controlled during the other half-bit,
- a resetting signal being supplied to the resetting input at every bit change,
- the counting clock input being fed with a counting clock whose frequency is a multiple of a carrier frequency of the carrier wave,
- the signal input being fed with the biphase modulated signal, and
- the time window input being fed with a time window signal which releases the AND circuit for a predetermined time portion of each carrier wave period in a predetermined phase interval with respect to the carrier wave.
Dependencies are inferred from the claim text.