Test simplifying circuit contained in digital integrated circuit
AssigneeKabushiki Kaisha Toshiba
InventorTakashi Yoshimori
Life of this patent
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Abstract
A test simplifying circuit is based on a compact test method which is a test method for applying a test pattern series generated from a random pattern generator to a digital circuit to be tested and at the same time for compressing a response output of the to-be-tested circuit by use of a data compactor, and determining the result of data compression. The memory circuits and input/output circuits originally contained in an integrated circuit are used as the random pattern generator and data compactor used for the test, and the random pattern generator and data compactor are reconstructed by the memory circuits and the input/output circuits.
Claims5
A test simplifying circuit provided in a digital integrated circuit, comprising:
- a random circuit formed of a combination circuit;
- a plurality of memory circuits, coupled to said random circuit, for transmitting data into and out from said random circuit in a non-test mode and for shifting data in series in a scan test mode;
- a plurality of external terminals;
- and
- a plurality of input/output circuits, respectively connected to said plurality of external terminals and to said plurality of memory circuits, for transmitting data into and out of said digital integrated circuit and said random circuit in the non-test mode, and for shifting data in series in the scan test mode,
- wherein at least one of said plurality of memory circuits together with at least one of said plurality of input/output circuits constitute a linear feedback shift register in the scan test mode.
Dependencies are inferred from the claim text.