Master ECL bias voltage regulator

A master voltage regulator, comprising:

• a master voltage regulator circuit having an output node coupled to an emitter of an output transistor for providing a first output potential regulated over a range of output currents;
• at least one slave voltage regulator connected to receive as an input the first output potential from the output node of the master voltage regulator and to provide a second output potential to at least one emitter coupled logic load coupled to an output of the slave voltage regulator;
• and
• the master voltage regulator circuit further including:
• first compensating means for compensating the first output potential for a temperature-related characteristic of the at least one emitter coupled logic load, the first compensating means including a first transistor having a base terminal coupled to a collector of the output transistor and an emitter terminal coupled in series with an output node of a second compensating means, the second compensating means compensating the first output potential for a temperature-related characteristic of the at least oen slave voltage regulator.

A method of supplying a reference potential to one or more emitter coupled logic (ECL) loads, comprising the steps of:

• generating a temperature-compensated master reference potential;
• supplying the master reference poential as an input to at least one slave voltage regulator;
• supplying the one or more emitter coupled logic loads with a reference potential output from the at least one slave voltage regulator;
• and
• wherein the step of generating a temperature-compensated master reference potential includes the steps of:
• compensating the master reference potential for a temperature-related characteristic of the one or more emitter coupled logic loads;
• and
• compensating the master reference potential for a temperature-related characteristic of the at least one slave voltage regulator.