Programmable delay circuit having n-stage capacitance elements

Abstract

A programmable delay circuit comprising input terminals supplied with input signals to be delayed; output terminals for delivering the delayed signals therefrom; resistance elements inserted between the input terminals and the output terminals; n-stage capacitance elements having capacitance values of C, ZC, 4C . . . 2.sup.n-1 C respectively (where C is a unit capacitance value) and each connected at one end thereof to the output ends of the resistance elements; and n-stage selection means for selectively applyign to the other ends of the n-stage capacitance elements either a signal having an opposite-phase or in-phase relation to the input signal, or a reference potential level. The delay circuit is capable of performing a control operation relative to any short delay time on the order of picosecond and still ensuring satisfactory linearity in the delay characteristics.

Dependencies are inferred from the claim text.