Configurable pulse generator, especially for implementing signal delays in semiconductor devices

In a semiconductor device, a plurality of configurable pulse generators for imposing delays on a plurality of signals entering, processed within or exiting the semiconductor device, each configurable pulse generator comprising:

• a first line receiving an input signal "s" entering, processed within or exiting the semiconductor device;
• a delay element connected to the first line and imposing a delay of time "t" on the input signal "s" and outputting the input signal "s" on a second line as delayed input signal "s(t)";
• a third line receiving a trigger signal;
• an edge detector connected to the third line and providing a pulse output signal for the time "t" on a fourth line to the delay element, in and only in response to occurrence of the trigger signal, and until the occurrence of a reset signal, for delaying outputting the input signal "s" onto the second line, and for providing a signal on a fifth line for the time "t";
• an oscillator connected to the fifth line and providing a stream of periodic clock pulses on a sixth line in and only in response to the signal on the fifth line;
• a programmable counter connected to the sixth line and counting the clock pulses on the sixth lien for the time "t", and providing on a seventh line a signal indicative of a predetermined number of clock pulses counted;
• a terminal count decoder connected to the seventh line, providing the reset signal on an eighth line to the edge detector for terminating the pulse output signal upon occurrence of a predetermined number of clock pulses equating with the time "t", causing the delay element to output the delayed input signal "s(t)", providing the reset signal on the eighth line to reset the counter, and allowing the pulse generator to impose a like delay on a subsequent signal entering, processed within or exiting the semiconductor device.