Circuit for testing the frequency of a clock in an electronic system

A clock frequency tester circuit for determining whether the frequency FB of a test signal produced by a clock to be tested has a value which is comprised within a predetermined range of values centered around the frequency FA of a reference clock signal produced by a reference clock wherein n is a predetermined parameter greater than 2 being characteristic of the accuracy of the tester, said tester receiving said reference clock signal and said test signal which frequency value is to be tested, said tester comprising:

• frequency mixer means having a first input connected to said reference clock, a second input connected to the clock to be tested, and an output which provides a mixed output signal;
• divide-by-n circuit means for dividing the frequency FA of the reference clock and providing a signal at an output thereof;
• phase frequency comparator means having two inputs and an output, said inputs respectively connected to the output of said divide-by-n circuit means and to said frequency mixer means, for generating an output signal which remains at a steady level whenever the output signal of said divide-by-n circuit means has a frequency which is higher than that of said frequency mixer means;
• divide-by-2 circuit means connected to said reference clock FA and having an output;
• second phase frequency comparator means with two inputs and an output, said inputs respectively connected to said clock to be tested and to the output of said divide-by-2 circuit means, for generating an output signal which remains at a steady level whenever the frequency of the test signal of the clock to be tested is higher than the frequency of the output signal of said divide-by-2 circuit means;
• and
• means for combining said output signals of said first and second phase frequency comparators such that an output signal is provided having a steady level only when said frequency FB is contained within the range between FA-FA/n and FA+FA/n.