Integrated circuit chip package

Abstract

A hermetically sealed package for one or more integrated circuit chips that is made of three metal, thick-film layers, and one dielectric, thick-film layer to form a mounting surface for the chip. The first applied metal layer includes the power plane, and the fan-out leads including power and ground leads. The dielectric layer overlays the power plane and includes an annular rectangle overlaying a portion of all the leads of the first layer and an outer boundary strip overlaying extreme ends of the leads. The second screened metallic layer serves as the ground plane, and electrically engages the ground leads of the first metallic layer and the extreme outer ends of the signal leads. A third metallic layer includes a metallic sealing ring on the annular portion of the dielectric layer spaced from the perimeter of the power and ground planes and a plurality of spaced test probe pads overlaying the boundary strip in electrical contact with the first metallic layer, and an optional pad of metal in the central chip mount area. The power and ground leads are provided in the same layer which permits them to be closely spaced without shorting due to misregistration. The grounded metallic sealing ring minimizes capacitive coupling between the outwardly extending leads.

Dependencies are inferred from the claim text.