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US 5,175,127 AGranted
Self-aligned interlayer contact process using a plasma etch of photoresist
AssigneeMicron Technology, Inc.
InventorMonte Manning
Life of this patent
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Abstract
Described is a method of forming a self-aligned contact to an underlying structure with fewer critical patterning steps. The invention uses an isotropic oxygen plasma etch of a resist layer and a subsequent oxide etch to expose an underlying conductive layer such as doped polycrystalline silicon. A second conductive layer formed thereupon contacts the exposed first conductive layer.
Claims16
A method of forming a contact during the manufacture of a semiconductor device, comprising the steps of:
- a) forming a first insulative layer over a semiconductor substrate;
- b) forming a first conductive layer over said first insulative layer;
- c) forming a second insulative layer over said first conductive layer;
- d) patterning an etch stop layer over said insulative layer;
- e) covering at least a portion of said etch stop layer and a portion of said second insulative layer with a patterned layer of photoresist and leaving other areas of said second insulative layer exposed;
- f) removing any exposed portions of said etch stop layer and said exposed areas of said second insulative layer and removing at least a portion of said first conductive layer underneath said exposed second insulative layer;
- g) isotropically removing said photoresist to expose additional portions of said second insulative layer;
- h) etching through said additionally exposed portions of said second insulative layer to expose said first conductive layer underneath said additionally exposed portions of said second insulative layer;
- and
- i) forming a second conductive layer over said exposed area of said first conductive layer, thereby contacting said first conductive layer with s id second conductive layer.
7 more elements
A method of electrically contacting two layers of conductive material during the manufacture of a semiconductor die, comprising the steps of:
- a) doping a semiconductor substrate;
- b) forming a first layer of insulation over said substrate;
- c) forming a first conductive layer over said first insulative layer;
- d) forming a second layer of insulation over said first conductive layer;
- e) patterning a etch stop layer over said second layer of insulation;
- f) patterning a layer of photoresist over said etch stop layer and said second layer of insulation;
- g) etching through said etch stop layer and said second layer of insulation;
- h) etching through said first conductive layer;
- i) eroding said photoresist, thereby decreasing a width of said photoresist and exposing a portion of said second insulative layer;
- j) etching through said second insulative layer to expose a portion of said first conductive layer;
- k) forming a second conductive layer over said first conductive layer to provide electrical contact therebetween.
8 more elements
Dependencies are inferred from the claim text.