Method for manufacturing a stacked capacitor DRAM semiconductor device

A method for manufacturing a stacked capacitor for use in a dynamic RAM semiconductor device, comprising the steps of:

• a) selectively growing a field oxide layer on a surface of a first conduction type semiconductor substrate to define an active region;
• b) providing a gate oxide layer on said active region in a gate electrode pattern;
• c) forming a first conductive layer according to the gate electrode pattern;
• d) doping said active region on said semiconductor substrate with an impurity of a second conduction type using said gate electrode pattern and said field oxide layer as a mask, thereby forming an impurity-doped region;
• e) forming a first insulating layer on the whole surface of said semiconductor substrate;
• f) etching selectively said first insulating layer to expose a surface of said impurity-doped region in a first location, thereby forming a first contact hole;
• g) etching said semiconductor substrate to a certain depth through said first contact hole to form a trench;
• h) growing an epitaxial layer down to the interior of said first contact hole, on an inside surface of said trench;
• i) forming a second conductive layer upon said epitaxial layer;
• j) patterning said second conductive layer to form a lower electrode of a capacitor;
• k) forming a dielectric layer on said second conductive layer;
• l) forming a third conductive layer on said dielectric layer;
• and
• m) patterning said third conductive layer to form an upper electrode of said capacitor.

A method for manufacturing a stacked capacitor for use in a dynamic RAM semiconductor device, comprising the steps of:

• a) selectively growing a field oxide layer on a surface of a first conduction type semiconductor substrate to define an active region;
• b) providing a gate oxide layer on said active region in a gate electrode pattern;
• c) forming a first conductive layer according to said gate electrode pattern;
• d) doping said active region of said semiconductor substrate with an impurity of a second conduction type using said gate electrode pattern and said field oxide layer as a mask thereby forming an impurity-doped region;
• e) forming a thick first insulating layer on the whole surface of said semiconductor substrate;
• f) etching selectively said thick first insulating layer to expose a surface of said impurity-doped region in a first location, thereby forming a first contact hole;
• g) growing an epitaxial layer on the exposed surface of said impurity-doped region in said first contact hole;
• h) forming a second conductive layer on said epitaxial layer and said thick first insulating layer, wherein a central region of said second conductive layer over said epitaxial layer is depressed;
• i) patterning said second conductive layer to form a lower electrode of a capacitor;
• j) forming a dielectric layer on said second conductive layer;
• k) forming a third conductive layer on said dielectric layer;
• and
• l) patterning said third conductive layer to form an upper electrode of said capacitor.

A method for manufacturing a stacked capacitor for use in a dynamic RAM semiconductor device, comprising steps of:

• a) selectively growing a field oxide layer on a surface of a first conduction type semiconductor substrate to define an active region;
• b) providing a gate oxide layer on said active region in a gate electrode pattern;
• c) forming a first conductive layer according to said gate electrode pattern;
• d) doping said active region of said semiconductor substrate with an impurity of a second conduction type using said gate electrode pattern and said field oxide layer as a mask, thereby forming an impurity-doped region;
• e) forming a thick first insulating layer on the whole surface of said semiconductor substrate;
• f) flattening said thick first insulating layer;
• g) etching selectively said thick first insulating layer to expose a surface of said impurity-doped region in a first location, thereby forming a first contact hole;
• h) growing an epitaxial layer on the exposed surface of said impurity-doped region in said first location, in said first contact hole until said epitaxial layer is at least level with said flattened thick first insulating layer;
• i) etching the whole face of said thick first insulating layer to a predetermined depth;
• j) forming a second conductive layer upon said epitaxial layer;
• k) patterning said second conductive layer to form a lower electrode of a capacitor, wherein a central portion of said second conductive layer projects upwards over said epitaxial layer;
• l) forming a dielectric layer on said second conductive layer;
• m) forming a third conductive layer on said dielectric layer;
• and
• n) patterning said third conductive layer to form an upper electrode of said capacitor.