Loading patent…
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMasahiro Yoneda
Estimating the term…
A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystaline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and ethcing the high melting point metal silicide layer by wet etching. The wet etching enables etching process without damaging the silicon substrate surface.
A method of manufacturing a semiconductor device having, on a semiconductor substrate, conductive layers for electrode of a laminated structure including a conductive layer containing a refractory metal and a polycrystalline silicon layer, comprising the steps of:
A method of manufacturing a semiconductor device having, on a semiconductor substrate, conductive layers for electrode of a laminated structure including a conductive layer containing a refractory metal and a polycrystalline silicon layer, comprising the steps of:
Dependencies are inferred from the claim text.