US 5,171,713 AGranted

Process for forming planarized, air-bridge interconnects on a semiconductor substrate

OwnerJames A. Matthewsinventor

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Abstract

A process for fabricating a integrated circuit (IC), including a plurality of devices coupled together by a system of metal interconnects disposed above a semiconductor substrate comprises the steps of forming a plurality of conductive pedestals on the surface of the substrate. A portion of the pedestals form electrical contacts to the devices, wherein the height of the pedestals is higher than any feature of the substrate. After a polyimide layer is deposited on the substrate to a thickness which covers the pedestals, an etching step is performed until the top surface of the pedestals is coplanar with the polyimide layer. A set of metal interconnect lines is then formed over the polyimide and pedestals to form electrical connections to selected ones of the pedestal contacts.

Claims17

Dependent claims

In a process for fabricating an integrated circuit (IC) which includes a plurality of devices coupled together by a system of metal interconnects, a method of forming said system above the surface of a semiconductor substate comprising the steps of:

(a) forming a plurality of conductive pedestals on said surface of said substrate, said plurality of pedestals including first and second portions wherein said first portion forms electrical contacts to said devices, said pedestals being formed to a predetermined height such that the top surface of said pedestals is higher that any feature of said substrate;
(b) depositing a first layer of polyimide over said substrate to a thickness which is sufficient to cover said pedestals;
(c) anisotropically etching said first polyimide layer until the upper surface of said first polyimide layer is roughly coplanar with said top surface of said pedestals;
and
(d) forming a first set of metal interconnect lines supported by said first and second portions of said pedestals over said first polyimide layer, said interconnect lines electrically coupling selected ones of said pedestals;
(e) forming via contacts on said metal interconnect lines;
(f) depositing a second layer of polyimide to completely cover said metal interconnect lines;
(g) anisotropically etching said second polyimide layer until the upper surface of said second polyimide layer is roughly coplanar with the top surface of said metal lines;
(h) forming a second set of metal interconnect lines over said second polyimide layer, thereby electrically coupling selected ones of said via contacts.

6 more elements

In a process for fabricating an integrated circuit (IC) comprising a plurality of semiconductor devices formed in a semiconductor substrate, a method of forming a planarized, air-bridge interconnect system disposed above the surface of said substrate comprising the steps of:

(a) forming a plurality of conductive pedestals on said surface of said substrate, said pedestals having a thickness such that the top surface of said pedestals is either substantially coplanar with, or higher than, the highest feature of said IC, a first portion of said pedestals forming electrical contacts to said devices and a second portion solely functioning as physical support members for said interconnect system;
(b) depositing a first layer of polyimide over said substrate to a thickness sufficient to cover said top surface of said pedestals;
(c) vertically etching said first polyimide layer until the upper surface of said first polyimide layer is approximately coplanar with said top surface of said pedestals;
(d) forming a first set of metal interconnect lines over said first polyimide layer, said lines electrically coupling selected ones of said pedestals;
(e) forming via contacts on said first set of metal interconnect lines;
(f) depositing a second layer of polyimide over said substrate to a thickness sufficient to cover said via contacts;
(g) vertically etching said second polyimide layer until the top surface of said second polyimide layer is approximately coplanar with the top surface of said via contacts;
(h) forming a second set of metal interconnect lines to electrically coupled selected ones of said via contacts;
(i) removing said first and second polyimide layers to create voids under said first and second sets of metal interconnect lines such that said first and second sets of lines are supported by said pedestals and said via contacts.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/647,718Filed 28 Jan 1991 · division
Priority: 10 Jan 1990
Granted: 15 Dec 1992
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 64/01346
On single crystalline silicon, e.g. chemical oxidation using a liquid: in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation…
H10D 64/0113
To Group IV semiconductors: the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
H10D 64/231
Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes: emitter or collector…
H10D 64/258
Source or drain electrodes for field-effect devices: characterised by the relative positions of the source or drain electrodes with respect to the…