Superconducting push-pull flux quantum digital logic circuits

A superconducting digital logic circuit comprising:

• a first circuit branch including first and second Josephson junctions electrically connected in series with each other;
• means for connecting a junction point between said first and second Josephson junctions to a neutral point;
• means for applying a positive bias voltage to a first end of said first circuit branch;
• means for applying a negative bias voltage to a second end of said first circuit branch;

A superconducting digital logic circuit comprising:

• a first circuit branch including first and second Josephson junctions electrically connected in series with each other;
• a first inductor electrically connected in series with a third Josephson junction for applying a first input signal, having a first polarity, to a first end of said circuit branch;
• a second inductor electrically connected in series with a fourth Josephson junction for applying a second input signal, having a second polarity, to a second end of said circuit branch;
• means for applying a positive bias voltage to said first end of said first circuit branch;
• means for applying a negative bias voltage to said second end of said first circuit branch;
• a second circuit branch including fifth, sixth, seventh, and eighth Josephson junctions electrically connected in series with each other;
• means for applying a positive synchronizing signal to a first end of said second circuit branch;
• means for applying a negative synchronizing signal to a second and of said second circuit branch;
• a third inductor electrically connected between said first end of said first circuit branch and a first junction point between said fifth and sixth Josephson junctions;
• a fourth inductor electrically connected between said second end of said first circuit branch and a second junction point between said seventh and eighth Josephson junctions;
• means for connecting a third junction point between said first and second Josephson junctions, and a fourth junction point between said sixth and seventh Josephson junctions to a neutral point;
• means for extracting a first output voltage signal from said first junction point;
• and
• means for extracting a second output voltage signal from said second junction point.

A superconducting digital logic circuit comprising:

• a first circuit branch including first, second, and third Josephson junctions electrically connected in series with each other;
• means for applying a positive bias voltage to a first end of said first circuit branch;
• means for applying a negative bias voltage to a second end of said first circuit branch;
• means for applying a first input voltage signal, having a first polarity, to a first node in said first circuit branch;
• means for extracting a first output voltage signal from a second node in said first circuit branch;
• means for applying said positive bias voltage to said second node in said first circuit branch;
• a second circuit branch including fourth and fifth Josephson junctions electrically connected in series with each other;
• means for applying said negative bias voltage to a first end of said second circuit branch;
• means for applying said negative bias voltage to a second end of said second circuit branch;
• means for applying a second input voltage signal, having a second polarity, to a first node in said second circuit branch;
• means for extracting a second output voltage signal from said second end of said second circuit branch;
• a sixth Josephson junction electrically connected to said second end of said second circuit branch;
• and
• means for applying said positive bias voltage to said sixth Josephson junction.

A method of performing digital logic in a superconducting circuit, said method comprising the steps of:

• applying a positive bias voltage to a first end of a first circuit branch including first and second Josephson junctions electrically connected in series with each other;
• applying a negative bias voltage to a second end of said first circuit branch;
• connecting a junction point between said first and second Josephson junctions to a neutral point;
• applying a first input voltage signal, having a first polarity, to said first end of said circuit branch;
• extracting a first output voltage signal from said first end of said circuit branch;
• applying a second input voltage signal, having a second polarity, to said second end of said circuit branch;
• and
• extracting a second output voltage signal from said second end of said circuit branch.

A method of synchronizing digital logic signals in a superconducting circuit, said method comprising the steps of:

• applying a positive bias voltage to a first end of a first circuit branch including first and second Josephson junction electrically connected in series with each other;
• applying a negative bias voltage to a second end of said first circuit branch;
• applying a first input signal, having a first polarity, to said first end of said circuit branch through a first inductor electrically connected in series with a third Josephson junction for;
• applying a second input signal, having a second polarity, to said second end of said circuit branch through a second inductor electrically connected in series with a fourth Josephson junction;
• applying a positive synchronizing signal to a first end of said second circuit branch including fifth, sixth, seventh, and eighth Josephson junctions electrically connected in series with each other;
• applying a negative synchronizing signal to a second end of said second circuit branch;
• connecting a third inductor between said first end of said first circuit branch and a first junction point between said fifth and sixth Josephson junctions;
• connecting a fourth inductor between said second end of said first circuit branch and a second junction point between said seventh and eighth Josephson junctions;
• connecting a third junction point between said first and second Josephson junctions, and a fourth junction point between said sixth and seventh Josephson junctions to a neutral point;
• extracting a first output voltage signal from said first junction point;
• and
• extracting a second output voltage signal from said second junction point.

A method of performing digital logic in a superconducting circuit, said method comprising the steps of:

• applying a positive bias voltage to a first end of first circuit branch including first, second, and third Josephson junctions electrically connected in series with each other;
• applying a negative bias voltage to a second end of said first circuit branch;
• applying a first input voltage signal, having a first polarity, to a first node in said first circuit branch;
• extracting a first output voltage signal from a second node in said first circuit branch;
• applying said positive bias voltage to said second node in said first circuit branch;
• applying said negative bias voltage to a first end of said second circuit branch including fourth and fifth Josephson junctions electrically connected in series with each other;
• applying said negative bias voltage to a second end of said second circuit branch;
• applying a second input voltage signal, having a second polarity, to a first node in said second circuit branch;
• extracting a second output voltage signal from said second end of said second circuit branch;
• and
• applying said positive bias voltage to said second end of said second circuit branch through a sixth Josephson junction.