US 5,166,926 AGranted

Packet address look-ahead technique for use in implementing a high speed packet switch

AssigneeBell Communications Research, Inc.

InventorsArturo Cisneros, Gary A. Hayward, Ivan P. Auer

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Abstract

Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). Each incoming packet cell has added thereto an additional header field containing information identifying a particular output module and a particular output port of that module. An input module associated with the switching crosspoints changes the additional header information to identify the particular output module of the next subsequent packet cell.

In apparatus for a packet switching system having "k" substantially identical input modules each providing "n" separate incoming lines and each having "m" separate outputs and "k" substantially identical output modules each having "m" separate inputs and providing "n" separate outgoing lines, said system also having "m" substantially identical k-by-k cross-point switching planes each having a plurality of switching elements and being connected to a corresponding one of the outputs of each of the input modules and to a corresponding one of the inputs to each of said output modules, wherein the corresponding output from every one of the input modules has the same numerical ranking and the corresponding input to every one of the output modules has the same numerical ranking ("k", "m", and "n" being pre-defined integer values), the method comprising the steps of:

appending a routing header to each input packet appearing over each of a plurality of input packet lines so as to form a corresponding incoming packet;
delivering said corresponding incoming packet to one of "m" outputs of one of said "k" input modules, wherein said routing header in said corresponding incoming packet appearing on said one output contains a routing address for a subsequent incoming packet that is to appear on said one output, said routing address having first and second routing address fields respectively containing an address of one of the "k" output modules and an address of one of the "n" outgoing lines provided by said one output module;
establishing, in response to said routing addresses contained in a first group of said incoming packets appearing on the corresponding output from all of said input modules, the configuration of said each cross-point switching plane prior to arrival on said corresponding output of all of said input modules of a second group of said incoming packets having input packets that are to be routed through said each cross-point plane in accordance with said routing addresses in said first group of incoming packets;
and
setting, in response to said establishing step, the states of said switching elements as defined by said configuration prior to routing said second group of incoming packets through said each cross-point plane.

2 more elements

Abstract

Claims14