Process for fabricating a silicon on insulator field effect transistor

#The present invention relates generally to semiconductors, and more particularly, to silicon on insulator (SOI) field effect transistors (FETs).

#From the beginning of the integrated circuit industry, the need for resistive devices and load resistors to operate as resistive pull-up devices has existed. A resistive pull-up device is a device connected to a main power supply of a transistor circuit and is needed to achieve high and low logic voltage levels. The early needs for a resistive pull-up device where satisfied by semiconductor resistive lines such as doped substrate-contained resistors and was improved upon much later in time by polysilicon resistor layers. The devices resulting from polysilicon and silicon loads were widely used but had several disadvantages, such as: (1) a large surface area and therefore poor circuit density; (2) a large amount of power consumption; (3) slow speed of operation; (4) a high occurrence of manufacturing-related inconsistencies and variation between die to die and wafer to wafer; (5) the inability to attain the consistently decreasing new dimensions required for performance improvements; and (6) higher leakage currents and other limitations.

#To improve upon performance and circuit density the industry began to research and adopt active load pull-ups which are gate biased thin-film transistors (TFTs) that act as voltage variable resistors. These gate biased TFTs provided several advantages: (1) a more power efficient replacement for resistive pull-ups, which was observed in the active load pull-up configuration in conventional complementary metal oxide semiconductor (CMOS) technology; (2) faster operational speed; (3) increased circuit density; and (4) submicron dimensional capability. As technology progressed, the TFTs used as pull-up structures developed the following limitations: (1) isolation problems such as the widely observed and understood latch-up phenomena; (2) increased leakage currents; (3) short channel behavior such as drain induced barrier lowering (DIBL) which adversely affects threshold voltages; (4) size reduction limitations; and (5) larger resistive losses. It was becoming apparent that a new technology was needed to further reduce structures beyond the conventional submicron sizes and to achieve higher levels of performance.

#FIGS. 1A-1C illustrate, in cross-sectional form, a semiconductor device fabrication process for forming a SOI FET in accordance with the present invention;

#FIG. 2 illustrates, in cross-sectional form, a SOI FET with a substrate contained gate region formed by a process in accordance with the present invention;

#FIG. 3 illustrates, in cross-sectional form, a SOI FET with an overlying gate region formed by a process in accordance with the present invention;

#As stated previously, the need exists for a process that can provide a resistive pull-up device with the advantages of: (1) isolation; (2) reduced dopant charge and impurity transfer between channel regions and a source and drain; (3) low temperature fabrication; (4) reduced resistive losses; (5) more repeatable manufacturing; (6) good support for contact metallurgy; and (7) reduction in unwanted short channel effects.

#Illustrated in FIGS. 1A-1C are cross-sectional diagrams which sequentially depict a process for forming a silicon on insulator (SOI) field effect transistor (FET) in accordance with the present invention. FIGS. 1A-1C illustrate a device 10 having all of the previously mentioned advantages. Device 10, in FIG. 1A, has a substrate 12, usually made of silicon but not limited to silicon, and an overlying dielectric layer 14. Dielectric layer 14 can be formed through one of several techniques, for example, growth or deposition. A substrate compatible layer doped to a predetermined density, in this case silicon layer 16, is formed overlying the dielectric layer 14. Silicon layer 16 will be used later in the process to form the SOI FET's channel region, which is a length of semiconductor material that separates a source current electrode and a drain current electrode. A germanium-silicon layer 18 is formed overlaying the silicon layer 16 and the germanium-silicon layer 18 will be used to form source and drain regions. The germanium-silicon layer 18 is made thicker than the underlying silicon layer 16 and in order to be selectively removed properly will hold a 20%-60% concentration of germanium for most applications. The germanium-silicon layer 18 may be doped with the appropriate source and drain impurity dopant atoms either in-situ, where impurities are introduced into a material during formation, or after formation with ion implantation or diffusion techniques. An optical nitride layer 20 is illustrated in FIG. 1A and is deposited for several reasons: (1) to act as a safety hard mask for the germanium-silicon etch step which tends to consume large amounts of photoresist; and/or (2) to help protect the underlying source and drain regions from implants; and/or (3) to add an extra dielectric layer between the subsequently formed source and drain and overlying regions to help reduce capacitive coupling such as Miller Capacitance. As stated previously, the nitride layer 20 is optional and may or may not be formed depending on the application and specific details of the manufacturing process.

#If the optional nitride layer 20 is formed, FIG. 1B illustrates a nitride removal step of a portion of nitride layer 20 on the germanium-silicon layer 18. To remove only a predetermined area of the nitride, a masking layer 22, usually photoresist, is formed over the nitride layer 20, usually through a conventional spin and bake procedure. A channel size region is exposed into the masking layer 22 through known photolithographic techniques and developed to form an opening in the masking layer 22. Conventional wet or dry etch technology can then be used to open the same channel size opening in the nitride layer 20.