High-density double-sided multi-string memory module with resistor for insertion detection

A memory module for installation on a motherboard, said memory module comprising:

• thirty-two memory integrated circuit chips, each having address, data, control, power and ground terminals;
• a multi-layer printed wiring board having address, data, control, power and ground wiring connected to said address, data, control, power and ground terminals of said memory integrated circuit chips;
• said printed wiring board also having a series of terminals disposed along an edge portion of said printed wiring board for connecting said address, data, control, power and ground wiring to said motherboard;
• said printed wiring board having six copper layers and five epoxy-fiberglass layers;
• and
• a plurality of decoupling capacitors mounted on said printed wiring board and connected to said power and ground wiring;
• wherein said thirty-two memory integrated circuit chips are arranged as a first rectangular matrix of two rows and eight columns of said memory integrated circuit chips on one side of said printed wiring board, and a second rectangular matrix of two rows and eight columns of said memory integrated circuit chips on an opposite side of said printed wiring board so that each integrated circuit chip in said first matrix is in registration with a corresponding integrated circuit chip in said second matrix;
• wherein said decoupling capacitors include a first row of eight decoupling capacitors aligned between the two rows of chips on one side of the printed wiring board, and a second row of eight decoupling capacitors aligned between the two rows of chips on the other side of the printed wiring board;
• wherein said control wiring includes a first row address strobe line, a second row address strobe line, a third row address strobe line, a fourth row address strobe line, a first column address strobe line and a second column address strobe line;
• said thirty-two memory integrated circuit chips include a first group of eight of said chips (a first "string") for which each chip in said first group has a row address strobe terminal connected to said first row address strobe line and a column address strobe terminal connected to said first column address strobe line, a second group of eight of said chips (a second "string") for which each chip in said second group has a row address strobe terminal connected to said second row address strobe line and a column address strobe terminal connected to said second column address strobe line, a third group of eight of said chips (a third "string") for which each chip in said third group has a row address strobe terminal connected to said third row address strobe line and a column address strobe terminal connected to said first column address strobe line, and a fourth group of eight of said chips (a fourth "string") for which each chip in said fourth group has a row address strobe terminal connected to said fourth row address strobe line and a column address strobe terminal connected to said second column address strobe line,
• wherein said address wiring includes a first address bus having a first set of address lines connecting in parallel address terminals of each chip in said first and third groups, and a second address bus separate from said first address bus, said second address bus having a second set of address lines connecting in parallel address terminals of each chip in said second and fourth groups;
• and
• wherein said data wiring includes a common data bus having data lines each of which is connected to a chip in said first group, a chip in said second group, a chip in said third group, and a chip in said fourth group.