Method of making a vertical current flow field effect transistor

A method for forming a transistor comprising the steps of:

• forming a structure comprising a first region of semiconductor material of a first dopant concentration and a first conductivity type, and a second region of semiconductor material of said first conductivity type and a second dopant concentration greater than said first dopant concentration formed on said first region;
• etching a plurality of grooves, said grooves extending through said second region and at least a portion of said first region;
• forming a plurality of insulating layers, each insulating layer within said plurality being formed in an associated one of said grooves, said insulating layers each having a first insulating region adjacent said first region having a first insulating region adjacent said first region of semiconductor material, said insulating layers each having a second insulating region adjacent said second region of semiconductor material, said second insulating region being thicker than said first insulating region;
• forming a gate structure within each of said grooves, said gate structure being insulated from said first and second regions by said insulating layers;
• and
• forming a plurality of semiconductor regions of a second conductivity type within said first region adjacent to said plurality of insulating layers for removing current carriers of said second conductivity type from said first region.

A method for manufacturing a transistor comprising the steps of:

• providing a structure comprising a first semiconductor region of a first conductivity type, a second semiconductor region of said first conductivity type on said first region, said second region having a dopant concentration less than a dopant concentration of said first region, a third semiconductor region of a second conductivity type opposite said first conductivity type formed on said second semiconductor region, and a fourth semiconductor region of said first conductivity type formed on said third semiconductor region;
• etching a trench through said fourth, third and second semiconductor regions;
• forming an insulating layer in said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said third semiconductor region;
• and
• forming a gate in said trench,
• wherein said insulating layer forming step comprises the steps of:
• masking sidewalls of said trench with a mask;
• forming an insulator on a surface of said trench below said mask;
• removing said mask from the sidewalls;
• and
• forming an insulator on a surface of said trench.

A method for manufacturing a transistor comprising the steps of:

• providing a structure comprising a first semiconductor region of a first conductivity type, a second semiconductor region of said first conductivity type on said first region, said second region having a dopant concentration less than a dopant concentration of said first region, a third semiconductor region of a second conductivity type opposite said first conductivity type formed on said second semiconductor region, and a fourth semiconductor region of said first conductivity type formed on said third semiconductor region;
• etching a trench through said fourth, third and second semiconductor regions;
• forming an insulating layer in said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said third semiconductor region;
• and
• forming a gate in said trench,
• wherein said etching step comprises the steps of:
• etching said trench through said fourth region;
• and
• extending said trench at least through said third region;
• and
• wherein said process further comprises, between said step of etching through said fourth region and said extending step, the step of forming a first insulator on walls of said trench.

A method of making a transistor comprising the steps of:

• providing a P-type first semiconductor region;
• providing a P-type second semiconductor region adjacent said first region, said second region having a dopant concentration less than a dopant concentration of said first region;
• providing an N-type third semiconductor region adjacent said second region;
• providing a P-type fourth semiconductor region adjacent said third region;
• etching a plurality of grooves through said fourth, third and second regions;
• forming an insulating layer in said grooves, a first portion of said insulating layer adjacent said first region being thicker than a second portion of said insulating layer adjacent said third region, said second portion being formed on sidewalls of said grooves;
• and
• forming a conductor in said grooves.

A method for making a transistor comprising the steps of:

• providing a first semiconductor region of a first conductivity type;
• providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region;
• forming a first groove in said second region;
• extending said first groove to at least said first region;
• forming a first insulator on a bottom of said first groove;
• forming a second insulator on the bottom and sidewalls of said first groove;
• and
• forming a first conductor in said groove,
• said method further comprising, between said groove forming and extending steps, the step of providing a third semiconductor region of a second conductivity type opposite said first conductivity type adjacent a bottom of said first groove and contained within said first portion.

A method for making a transistor comprising the steps of:

• providing a first semiconductor region of a first conductivity type;
• providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region;
• forming a first groove in said second region;
• extending said first groove to at least said first region;
• forming a first insulator on a bottom of said first groove;
• forming a second insulator on the bottom and sidewalls of said first groove;
• and
• forming a first conductor in said groove,
• wherein the step of forming the first insulator comprises the steps of:
• depositing a mask on a surface of said groove;
• etching said mask by a vertical etching process until at least a portion of said mask is removed from the bottom of said groove;
• and
• forming an insulator on the bottom of said groove.

A method for making a transistor comprising the steps of:

• providing a first semiconductor region of a first conductivity type;
• providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region;
• forming a first groove in said second region;
• extending said first groove to at least said first region;
• forming a first insulator on a bottom of said first groove;
• forming a second insulator on the bottom and sidewalls of said first groove;
• and
• forming a first conductor in said groove, said method further comprising, prior to said groove forming step, the steps of:
• forming a third insulator on said second region;
• and
• forming a mask on said third insulator;
• and wherein said method further comprises the steps of:
• forming a fourth insulator thicker than said third insulator over said conductor;
• forming an opening through said fourth insulator to said gate;
• removing said mask;
• etching said third and fourth insulators until said third insulator is removed;
• and
• forming a conductor in said opening and on said second region.

A method for making a transistor comprising the steps of:

• providing a first semiconductor region of a first conductivity type;
• providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region;
• forming a first groove in said second region;
• extending said first groove to at least said first region;
• forming a first insulator on a bottom of said first groove;
• forming a second insulator on the bottom and sidewalls of said first groove;
• and
• forming a first conductor in said groove,
• wherein said second region comprises a second portion having a dopant concentration higher than the dopant concentration of said first portion, and
• wherein said groove forming step comprises the steps of:
• forming a groove through said second portion;
• forming an insulator on walls of said groove through said second portion;
• and
• extending said groove.