Video display system using memory with parallel and serial access employing serial shift registers selected by column address

A dual port memory circuit having provision for both serial and random access, comprising

• a memory component having a plurality of cells arranged in rows and columns interconnected by lines therein,
• a serial register means having a plurality of bit positions each corresponding to and interconnectable with one of said column lines in said memory component,
• a plurality of taps each interconnected with said register means at a different one of said bit positions thereon,
• row address means interconnected with said memory component for selecting one of said row lines therein,
• column address means interconnected with said memory component for selecting one of said column lines or one of said taps, and
• output terminal means interconnected with said register means at a selected one of said taps in response to said column address means.

An improved video-type computer system, comprising

• a data processing circuit for generating video data bits and a column address signal,
• a memory circuit having a plurality of cells interconnected in rows and columns and responsive to said column address signal for receiving said video data bits,
• a shift register having a plurality of bit positions for receiving stored video data bits from related columns of cells in said memory circuit,
• a plurality of taps each interconnected with said shift register at preselected bit positions, and
• selection means responsive to said column address signal for selecting one of said taps and unloading video data bits from a functionally related portion of said shift register.

A dual port memory circuit arranged for both serial access and random access, the memory circuit comprising:

• a memory component having an array including a plurality of cells arranged in rows and columns,
• a serial register having a plurality of storage elements, each corresponding to one of the columns of the array, the plurality of storage elements being selectively connectable to the columns of cells,
• a plurality of taps, each interconnected with a different storage element of the serial register,
• a row address circuit interconnected with the array for accessing a selected one of the rows of cells,
• a terminal, and
• a column address circuit interconnected with the memory component either for randomly accessing a selected one of the columns of cells or for selecting one of the taps for coupling a serial stream of data to the terminal.

A video display system comprising:

• a data processor generating row addresses, column addresses, control signals and data bits representing an image,
• a display device responsive to video signals for producing a visual image,
• a dual port memory device arranged for both random and serial access for inputting data bits and outputting data bits, the memory device including
• a plurality of cells arranged in rows and columns,
• a serial register having a plurality of storage elements, each storage element corresponding to one of the columns of the memory components, and having a plurality of taps, each tap associated with a different one of the storage elements,
• a row address circuit interconnected with the rows of cells for accessing a selected one of the rows of cells for writing or reading of data,
• a column address circuit interconnected with the columns of cells for randomly accessing data stored in a selected column of cells and interconnected with the taps for serial access of the data stored in the serial register commencing at a selected storage element, and
• a video signal shaping circuit, responsive to the serial data from the serial register, for producing the video signal and applying the video signal to the display device.

A storage device adapted for both random access and serial access modes of operation and responsive to a row address signal, a row access strobe signal, a column address signal, a column access strobe signal, and a transfer signal, the storage device comprising:

• a memory array having cells arranged in addressable rows selectable in response to said row address signal, and said row access strobe signal and in addressable columns selectable in response to said column address signal and said column access strobe signal;
• register means having a plurality of bit positions which are interconnectable with or disabled from connecting with said columns of said memory array in response to states of said transfer signal and having a plurality of taps adjacent preselected bit locations therealong;
• and
• tap selection means interconnected with the register means for selecting one of said taps in conjunction with said column address signal and said column access strobe signal.

A dual port memory circuit arranged for both serial access and random access, the memory circuit comprising:

• a memory array having a plurality of cells arranged in addressable rows and columns;
• a register having a plurality of storage elements, each storage element corresponding to one of the columns of the memory array, the plurality of storage elements being selectively connectable to the columns of cells;
• a row address circuit interconnected with the memory array for randomly accessing a selected one of the rows of cells;
• a column address circuit interconnected with the memory array for randomly accessing a selected one of the columns of cells;
• a terminal interconnected with the register for writing a serial stream of data into the register;
• the row address circuit accessing a first selected row of cells for storing the serial stream of data from the register;
• and
• the row address circuit accessing a second selected row of cells for storing the same serial stream of data from the register without rewriting the serial stream of data into the register.

A memory circuit comprising:

• a memory array having a plurality of cells arranged in addressable rows and columns;
• a register having a plurality of storage elements, each storage element corresponding to one of the columns of the memory array, the plurality of storage elements being selectively connectable to the columns of cells;
• a row address circuit interconnected with the memory array for randomly accessing a selected one of the rows of cells;
• a column address circuit interconnected with the memory array for randomly accessing a selected one of the columns of cells;
• the row address circuit accessing a first selected row of cells for transferring the selected row of data out of the cells into the register;
• and
• the row address circuit accessing a second selected row of cells for transferring the data from the register into the second selected row of cells.

A video display system comprising:

• a data processor generating row addresses, column addresses, control signals, and data bits representing an image;
• a display device responsive to a serial sequence of data bits for producing a visual image;
• a dual port memory device arranged for both random access for inputting data bits from the data processor and serial access for outputting data bits to the display device, the memory device including:
• an array of storage cells positioned in addressable rows and columns;
• a register including a plurality of storage elements and a plurality of taps;
• a transfer circuit, responsive to a transfer signal, for enabling coupling between the storage elements and the storage cells;
• row access circuitry, accessed contemporaneously with the transfer circuit, for transferring data bits from a row of storage cells to the storage elements;
• tap access circuitry, responsive to a column address and a column address strobe, for selecting one of the taps for coupling the register to the display device;
• and
• the register responsive to a clock signal for delivering a serial sequence of the data bits from the register by way of the selected tap to the display device for producing the visual image.

A memory arrangement comprising:

• an array of storage cells positioned in addressable rows and columns;
• a register including a plurality of storage elements and a plurality of taps;
• a transfer circuit, responsive to a transfer signal, for enabling coupling between the storage elements and the storage cells;
• row access circuitry accessed contemporaneously with the transfer circuit for transferring data from a row of storage cells to the storage elements;
• tap access circuitry, responsive to a column address and a column address strobe, for selecting one of the taps for coupling the register to a serial data terminal;
• and
• the register responsive to a clock signal for delivering a serial sequence of data by way of the selected tap to the serial data terminal.