Semiconductor cell memory with current sensing

A semiconductor memory, comprising:

• a memory cell array including a plurality of memory cells;
• BIT lines and word lines connecting said memory cells in a matrix;
• a sense circuit including a plurality of current source means, each of said current source means being connected with a corresponding one of said BIT lines for providing BIT line drive current flowing into or out of said corresponding BIT lines, so that said BIT line drive current is larger than said constant cell current in said corresponding BIT Lines;
• means for selecting said BIT lines including switching them from unselected to selected states;
• said memory cells each being connected with a pair of said BIT lines;
• each of said memory cells having first means for feeding said constant cell current as I.sub.cell to one of said BIT lines of said pair in accordance with stored information when at least said pair of BIT lines are selected;
• said current source means feeding the BIT line drive current as I.sub.R at least transiently to the pair of BIT lines switched from unselected to selected states;
• said sense circuit including sense amplifier means for detecting the difference between the currents flowing in said selected pair of BIT lines to read out the stored information, wherein said BIT line drive current I.sub.R and said constant cell current I.sub.cell have a relation of I.sub.R >I.sub.cell ;
• each of said memory cells includes a flipflop having first and second insulated gate type transistors having their gates and drains cross-coupled with each other, and third and fourth insulated gate type transistors coupled to said BIT lines;
• means for feeding read control signals;
• a pair of bipolar transistors respectively connected between said BIT lines and said sense amplifier means and having emitters connected with said BIT lines, bases fed by said means for feeding read control signals and collectors connected with said sense amplifier means;
• and
• means connected between said BIT lines and said sense amplifier means for feeding an additional current substantially equal to said current I.sub.R for reducing noise.

A semiconductor memory, comprising:

• a memory cell array including a plurality of memory cells;
• BIT lines and word lines connecting said memory cells in a matrix;
• a sense circuit including a plurality of current source means, each of said current source means being connected with a corresponding one of said BIT lines for providing BIT line drive current flowing into or out of said corresponding BIT lines, so that said BIT line drive current is larger than said constant cell current in said corresponding BIT Lines;
• means for selecting said BIT lines including switching them from unselected to selected states;
• said memory cells each being connected with a pair of said BIT lines;
• each of said memory cells having first means for feeding said constant cell current as I.sub.cell to one of said BIT lines of said pair in accordance with stored information when at least said pair of BIT lines are selected;
• said current source means feeding the BIT line drive current as I.sub.R at least transiently to the pair of BIT lines switched from unselected to selected states;
• said sense circuit including sense amplifier means for detecting the difference between the currents flowing in said selected pair of BIT lines to read out the stored information, wherein said BIT line drive current I.sub.R and said constant cell current I.sub.cell have a relation of I.sub.R >I.sub.cell ;
• means for selecting said word lines;
• and
• wherein each of said memory cells includes means for feeding said cell current I.sub.cell to one of said BIT lines of said pair of BIT lines only when said word and BIT lines of said memory cell are selected.

A semiconductor memory, comprising:

• a memory cell array including a plurality of memory cells;
• BIT lines and word lines connecting said memory cells in a matrix;
• a sense circuit including a plurality of current source means, each of said current source means being connected with a corresponding one of said BIT lines for providing BIT line drive current flowing into or out of said corresponding BIT lines, so that said BIT line drive current is larger than said constant cell current in said corresponding BIT Lines;
• means for selecting said BIT lines including switching them from unselected to selected states;
• said memory cells each being connected with a pair of said BIT lines;
• each of said memory cells having first means for feeding said constant cell current as I.sub.cell to one of said BIT lines of said pair in accordance with stored information when at least said pair of BIT lines are selected;
• said current source means feeding the BIT line drive current as I.sub.R at least transiently to the pair of BIT lines switched from unselected to selected states;
• said sense circuit including sense amplifier means for detecting the difference between the currents flowing in said selected pair of BIT lines to read out the stored information, wherein said BIT line drive current I.sub.R and said constant cell current I.sub.cell have a relation of I.sub.R >I.sub.cell ;
• first and second constant voltage sources;
• a circuit supply voltage;
• wherein each of said memory cells further includes first and second loads connected between with the drains of said first and second insulated gate type transistors and said first constant voltage source;
• wherein said first and second insulated gate type transistors have their sources connected to said second constant voltage source;
• wherein the voltage difference V.sub.cell between the voltage of said first constant voltage source and said second constant voltage source is smaller than said circuit supply voltage;
• and wherein
• said voltage difference V.sub.cell satisfies the relation:
• I.sub.cell.>/=.beta.[k(I-k/2)V.sub.cell.sup.2 -kV.sub.T V.sub.cell ]
• wherein:
• .beta.:
• the .beta. value of the first and second insulated gate type transistors;
• V.sub.T :
• the threshold voltage of the first and second insulated gate type transistors;
• and
• k:
• the ratio of the first and second constant voltages, applied between the sources and drains of the first and second transistors.

A semiconductor memory, comprising:

• a memory cell array including a plurality of memory cells;
• BIT lines and word lines connecting said memory cells in a matrix;
• a sense circuit including a plurality of current source means, each of said current source means being connected with a corresponding one of said BIT lines for providing BIT line drive current flowing into or out of said corresponding BIT lines, so that said BIT line drive current is larger than said constant cell current in said corresponding BIT lines;
• means for selecting said BIT lines including switching them from unselected to selected states;
• said memory cells each being connected with a pair of said BIT lines;
• each of said memory cells having first means for feeding said constant cell current as I.sub.cell to one of said BIT lines of said pair in accordance with stored information when at least said pair of BIT lines are selected;
• said current source means feeding the BIT line drive current as I.sub.R at least transiently to the pair of BIT lines switched from unselected to selected states;
• said sense circuit including sense amplifier means for detecting the difference between the currents flowing in said selected pair of BIT lines to read out the stored information, wherein said BIT line drive current I.sub.R and said constant cell current I.sub.cell have a relation of I.sub.R >I.sub.cell by a ratio of I.sub.R to I.sub.cell that is greater than 2;
• and
• said sense amplifier means includes at least two current-voltage converter loads and two differential amplifiers operatively connected to said loads to amplify current differences in said pair of BIT lines and eliminate noise.