Multi-state EEprom read and write circuits and techniques
AssigneeSunDisk Corporation
InventorsSanjay Mehrotra, Eliyahou Harari, Winston Lee
Life of this patent
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AssigneeSunDisk Corporation
InventorsSanjay Mehrotra, Eliyahou Harari, Winston Lee
Estimating the term…
Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.
A circuit for sensing a test current relative to a plurality of predetermined current levels, comprising:
A circuit for sensing a test current relative to a plurality of predetermined reference current levels, each of the plurality of reference current levels being scalable by a multiplication factor from that of a lowest reference current level thereof, comprising:
A circuit for sensing a test current relative to a plurality of predetermined reference current levels, each of the plurality of reference current levels being scalable by a multiplication factor from that of a given reference current level thereof, comprising:
In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system resulting in a definite memory state having a corresponding threshold of conduction current relative to one or more predetermined threshold current levels used to demarcate memory states, and an erase electrode capable of removing charge from said floating gate, and said memory system including a reading system for determining the programmed state of an addressed cell, said reading system comprising:
Dependencies are inferred from the claim text.