Stacked solid via formation in integrated circuit systems
AssigneeHewlett-Packard Company
InventorsJacques Leibovitz, Maria L. Cobarruviaz, Kenneth D. Scholz, Clinton C. Chao
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Abstract
A method of forming solid copper vias in a dielectric layer permits stacked vias in a multi-chip carrier. A dielectric layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in the dielectric layer is filled with copper by deposition to form a hollow via. Using a photoresist mask, the hollow via is filled solid by electroplating a second amount of copper. The photoresist is then stripped and excess copper extending from the via is polished flat. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked vias.
Claims6
A method of forming an integrated circuit structure including solid vias, said method comprising the sequential steps of;
- a) forming a first circuit pattern on a substrate;
- b) depositing a first dielectric layer;
- c) defining apertures in said first dielectric layer;
- d) depositing a first metallization layer so as to form an upper conductive layer including a plurality of first dielectric layer vias through said apertures, said first dielectric layers being initially hollow, said first metallization layer consisting of a metal conductive layer sandwiched between metal adhesive layers which facilitate bonding to adjacent dielectric layer vias;
- e) depositing a photoresist layer on the structure resulting from step d) and defining apertures in said photoresist layer;
- f) filing said first dielectric layer vias with solid material so that said first dielectric layer vias become solid;
- and
- g) removing the remainder of said photoresist layer.
A method of forming an integrated circuit structure including solid vias, said method comprising the sequential steps of:
- a) forming a first circuit pattern on a substrate;
- b) depositing a first dielectric layer;
- c) defining apertures in said first dielectric layer;
- d) depositing a first metallization layer so as to form an upper conductive layer including a plurality of first dielectric layer vias through said apertures, said vias being initially hollow, said first metallization layer including a metal conductive layer sandwiched between metal adhesive layer;
- e) depositing a photoresist layer on the structure resulting from step d) and defining apertures in said photoresist layer;
- f) filling said first dielectric layer vias with conductive material so that said first dielectric layer vias become solid;
- g) polishing the structure resulting from step f so as to remove excess solid conductive material so that a composite conductive layer with a planar top surface and integral solid vias remains;
- and
- h) photolithographically patterning said composite conductive layer so as to define a first upper layer of conductive traces.
Dependencies are inferred from the claim text.