Method of fabricating IIL and vertical complementary bipolar transistors

A method of fabricating a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL, comprising the steps of;

• forming in a one-conductivity type semiconductor substrate a reverse-conductivity type first buried layer;
• forming in said first buried layer a one-conductivity type second buried layer;
• forming on said semiconductor substrate having said first and second buried layers a reverse-conductivity type first semiconductor layer;
• forming in said first semiconductor layer a one-conductivity type first diffused layer coming into contact with said second buried layer;
• forming in said first diffused layer a reverse-conductivity type second diffused layer coming into contact with said second buried layer, formed in singularity or plurality;
• forming a one-conductivity type third diffused layer at a position set apart in the lateral direction with respect to said first diffused layer;
• forming in said first semiconductor layer a groove that reaches said first buried layer, so formed as to surround the sides of said first diffused layer and said third diffused layer on their sides other than their sides opposed to each other;
• forming an insulating film only on each side wall of said groove;
• and
• filling said groove with a reverse-conductivity type second semiconductor layer so as to be connected with said first buried layer at the bottom of said groove;
• said first buried layer being made to serve as an emitter of the IIL, said second buried layer and said first diffused layer as the base of the IIL, said second diffused layer as a collector of the IIL, said third diffused layer as an injector of the IIL, and said second semiconductor layer as an emitter lead-out electrode of the IIL;
• the impurity density of the base right beneath the collector being lower than the impurity density of the emitter;
• and the impurity density of the base being made to monotonously become lower from the emitter toward the collector.

A method of fabricating a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL, comprising the steps of;

• forming in a one-conductivity type semiconductor substrate a reverse-conductivity type first buried layer;
• forming in said first buried layer a one-conductivity type second buried layer;
• forming on said semiconductor substrate having said first and second buried layers a reverse-conductivity type first semiconductor layer;
• forming in said first semiconductor layer a one-conductivity type first diffused layer coming into contact with said second buried layer;
• forming a one-conductivity type third diffused layer at a position set apart in the lateral direction with respect to said first diffused layer;
• forming in said first diffused layer a groove that substantially reaches said second buried layer, formed in singularity or plurality;
• forming an insulating film only on each side wall of said groove;
• filling said groove with a reverse-conductivity type second semiconductor;
• and
• forming a reverse-conductivity type second diffused layer coming into contact with said second buried layer, by causing a reverse-conductivity type impurity to diffuse from said second semiconductor layer;
• said first buried layer being made to serve as an emitter of the IIL, said second buried layer and said first diffused layer as the base of the IIL, said second diffused layer as a collector of the IIL, said third diffused layer as an injector of the IIL, and said second semiconductor layer as a collector lead-out electrode of the IIL;
• the impurity density of the base right beneath the collector being lower than the impurity density of the emitter;
• and the impurity density of the base being made to monotonously become lower from the emitter toward the collector.