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AssigneeXicor, Inc.
InventorsWilliam H. Owen, John Caywood, Joseph Drori, James Jaffe, Isao Nojima, Jeffrey Sung, Ping Wang
Estimating the term…
A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundancy apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.
In an integrated circuit memory array including a plurality of primary memory cells, each said primary memory cell for storing data, a redundant memory cell for storing data, address means for enabling each of said primary memory cells to be accessed when a corresponding unique address is coupled thereto on a plurality of address lines, said address means using standard binary logic voltage levels when coupling said unique address onto said address lines, and binary logic voltage levels when coupling said unique address onto said address lines, and read/write means for reading data from and for writing data to each said primary memory cell on a plurality of data lines when the address of said primary memory cell is coupled to said address means, said read/write means using standard binary logic voltage levels for data states on said data lines, a field-programmable redundancy system for enabling said integrated circuit memory array to temporarily enter a special reconfiguration mode for replacing a selected one of said primary memory cells with said redundant memory cell such that data is exchanged by said read/write means with said redundant memory cell when the address of said replaced primary memory cell is coupled to said address means, comprising:
In an integrated circuit memory array having a plurality of primary memory cells and a redundant memory cell, address lines for selectively addressing each of said primary memory cells and one or more data lines for writing of data to or read out of data from each said primary memory cell when that cell has been selectively addressed, a method for replacing a defective one of said primary memory cells with said redundant memory cell comprising the steps of:
In an integrated circuit memory array including a plurality of primary memory cells, each said primary memory cell for storing data, at least one redundant memory cell for storing data, address means for enabling each of said primary memory cells to be accessed when a corresponding unique address is coupled thereto on a plurality of address lines, said address means using standard binary logic voltage levels when coupling said unique address onto said address lines, and read/write means for reading data from and for writing data to each said primary memory cell on a plurality of data lines when the address of said primary memory cell is coupled to said address means, said read/write means using standard binary logic voltage levels for data states on said data lines, a field-programmable redundancy system for enabling said integrated circuit memory array to temporarily enter a special reconfiguration mode for replacing a selected one of said primary memory cells with one of said redundant memory cells such that data is exchanged by said read/write means with said redundant memory cell when the address of said replaced primary memory cell is coupled to said address means, comprising:
In an integrated circuit memory array having a plurality of primary memory cells and at least one redundant memory cell, address lines for selectively addressing each of said primary memory cells and one or more data lines for writing of data to or reading out of data from each said primary memory cell when that cell has been selectively addressed, a method for replacing a defective one of said primary memory cells with a selected one of said redundant memory cells comprising the steps of:
Dependencies are inferred from the claim text.