Overcurrent-detection circuit

An overcurrent-detection circuit comprising:

• a semiconductor power MOSFET having drain, source and gate terminals:
• a current-mirror device having a drain terminal connected in common with said power-MOSFET drain terminal, a gate terminal connected in common with said power-MOSFET gate terminal, and a shunt-current terminal, said current-mirror device arranged for conducting a shunt current between said drain terminal and said shunt-current terminal when current flows between said drain and source terminals of said power MOSFET:
• a depletion-type MOSFET having source and gate terminals connected in common with said source terminal of said power MOSFET, and a drain terminal connected in common with said shunt-current terminal, said depletion-type MOSFET arranged as a constant-current device for maintaining a shunt current through said depletion-type MOSFET at a substantially constant level, after said shunt current rises to a predetermined level;
• determining means, including a constant-voltage device and a comparator coupled in series across said depletion-type MOSFET for providing an overcurrent signal when the voltage drop across said constant-current device exceeds a predetermined voltage generated by said constant-voltage device;
• a drive circuit, coupled to said gate terminal of said power MOSFET, for determining current flow through said power MOSFET;
• and
• a control circuit, coupled to said drive circuit, for generating an overcurrent-control signal responsive to said overcurrent signal and coupling said overcurrent-control signal to said drive circuit;
• whereby said overcurrent-control signal may be used to control said power MOSFET to avoid damage from overcurrents.

An overcurrent-detection circuit comprising:

• a semiconductor power device having first and second main-current terminals and a control terminal, which semiconductor power device is subject to damage from an overcurrent;
• a current-mirror device having a first terminal connected in common with said first main-current terminal, a control terminal connected in common with said control terminal of said semiconductor power device, and a shunt-current terminal , and arranged for conducting a shunt current between said first terminal and shunt-current terminal of said current-mirror device when current flows between said first and second main-current terminals;
• constant-current means, comprising a first enhancement-type MOSFET having a source terminal coupled to said second main-current terminal, a drain terminal coupled to said shunt-current terminal and a gate terminal, for maintaining a shunt current through said constant-current means at a substantially constant level, after said shunt current rises to a predetermined level;
• determining means, coupled across said constant-current means and responsive to changes in voltage drop across said constant-current means, for providing an overcurrent-control signal when the voltage drop across said constant-current means exceeds a predetermined voltage;
• and
• a gate-bias circuit, coupled across said constant-current means, including:
• a second enhancement-type MOSFET having source and gate terminals respectively coupled to said source and gate terminals of said first enhancement-type MOSFET, and a drain terminal;
• a zener diode coupled across said source and drain terminals of said second enhancement-type MOSFET;
• and
• a constant-voltage source coupled across said zener diode;
• whereby, said overcurrent-control signal may be used to control said semiconductor power device to avoid damage from overcurrents and said gate-bias circuit introduces temperature-dependent operating variations which tend to offset such Variations inherently affecting operation of said constant-current means.

An overcurrent-detection circuit comprising:

• a semiconductor power MOSFET having drain, source and gate terminals:
• a current-mirror device having a drain terminal connected in common with said power-MOSFET drain terminal, a gate terminal connected in common with said power-MOSFET gate terminal, and a shunt-current terminal, said current-mirror device arranged for conducting a shunt current between said drain terminal and said shunt-current terminal when current flows between said drain and source terminals of said power MOSFET:
• a first enhancement-type MOSFET having a source terminal connected in common with said power-MOSFET source terminal, a drain terminal connected in common with said shunt-current terminal, and a gate terminal, said enhancement-type MOSFET arranged as a constant-current device for maintaining a shunt current through said enhancement-type MOSFET at a substantially constant level, after said shunt current rises to a predetermined level;
• determining means, including a constant-voltage device and a comparator coupled in series across said enhancement-type MOSFET, for providing an overcurrent signal when the voltage drop across said constant-current means exceeds a predetermined voltage generated by said constant-voltage device;
• a drive circuit, coupled to said gate terminal of said power MOSFET, for determining current flow through said power MOSFET;
• a control circuit, coupled to said drive circuit, for generating an overcurrent-control signal responsive to said overcurrent signal and coupling said overcurrent-control signal to said drive circuit;
• and
• a gate-bias circuit, coupled across said first enhancement-type MOSFET, including:
• a second enhancement-type MOSFET having source and gate terminals respectively coupled to said source and gate terminals of said first enhancement-type MOSFET, and a drain terminal;
• a zener diode coupled across said source and drain terminals of said second enhancement-type MOSFET;
• and
• a constant-voltage source coupled across said zener diode;
• whereby said overcurrent-control signal may be used to control said power MOSFET to avoid damage from overcurrents and said gate-bias circuit introduces temperature-dependent operating variations which tend to offset such variations inherently affecting operation of said first enhancement-type MOSFET.