Time difference correction circuit for brightness and chrominance signals

A time difference correction circuit for brightness and chrominance signals which divides a signal from a tape detected through a head into a brightness signal and a chrominance signal, said circuit comprising:

• delay means for delaying the chrominance signal by a predetermined horizontal interval;
• a vertical synchronizing signal generation means for detecting a vertical synchronizing signal from said brightness signal and delaying it to a start point of a video signal;
• a switching means for switching said brightness and chrominance signals at the start point of the video signal;
• a comparison means for comparing the brightness and chrominance signals applied through said switching means and for amplifying a difference between them by a predetermined amplification factor;
• a difference signal generation means for sampling an output signal of said comparison means in the form of a specific wave to generate a predetermined level corresponding to a difference between the brightness and chrominance signals, amplifying the difference by a predetermined amplification factor and holding it to a start point of a next field;
• a time difference signal detection means for detecting a time difference between the brightness and chrominance signals using the output of said comparison means and holding a polarity signal corresponding to the time difference to the start point of the next field;
• an invertor means for inverting polarity of the output of said difference signal generation means by using the polarity signal of said time difference signal detection means as a control signal;
• a reset means for differentiating an output signal of said vertical synchronizing signal generation means and outputting only a positive component of the differentiated signal corresponding to a single field interval to said difference signal generation means as a control signal;
• and
• a voltage controlled oscillator for increasing and decreasing oscillating frequency by an amount corresponding to level and polarity of an output signal of said invertor means and outputting said oscillating frequency to said delay means as a clock frequency.