Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line

A circuit for generating a plurality of timing signals, comprising in combination:

• (a) a plurality of cascade-connected delay cells, each except a first or having an input coupled to an output of another;
• (b) a plurality of latches each having a set input, a reset input, and an output;
• (c) first means for coupling a set input of a first latch to an output of a first delay cell to determine a time of occurrence of a leading edge of a timing pulse produced at the output of the first latch;
• (d) second means for coupling a reset input of the first latch to an output of a second delay cell to determine a time of occurrence of a trailing edge of a timing pulse produced at the output of the first latch;
• (e) a phase detector having a first input coupled to receive a clock signal and a second input coupled to an output of a second delay cell to receive a signal indicating propagation of a logic state through the first and second delay cells, and means in the phase detector for producing an adjustment signal indicative of whether the phase of the indicating signal is ahead of or behind the phase of the clock signal;
• (f) means responsive to the clock signal for initiating propagation of the logic state through the delay cells;
• and
• (g) means in each of the delay cells for increasing or decreasing a delay of that delay cell in response to the adjustment signal to cause a time required for the logic state to propagate through the predetermined number of the delay cells to be equal to a period of the clock signal.

A circuit for generating a plurality of timing signals, comprising in combination:

• (a) a tapped delay line having a plurality of sequentially connected delay sections, each having a corresponding output;
• (b) first means for determining a time of occurrence of a leading edge of a timing signal in response to an output of one of the delay sections;
• (c) second means for determining a time of occurrence of a trailing edge of a timing signal in response to an output of another of the delay sections;
• (d) a phase detector having a first input coupled to receive a clock signal and a second input coupled to an output of a section of the delay line to receive a signal indicating propagation of a logic state through the section of the delay line, and means in the phase detector for producing an adjustment signal indicative of whether the phase of the indicating signal is ahead of or behind the phase of the clock signal;
• (e) means responsive to the clock signal for initiating propagation of the logic state through the delay line;
• and
• (f) means in each of the plurality of sequentially connected delay sections for increasing or decreasing a delay of that sections in response to the adjustment signal to cause a time required for the logic state to propagate through the sequentially connected delay sections to be equal to a period of the clock signal.

A method for generating a plurality of timing signals, comprising steps of:

• (a) initiating propagation of a logic state through a tapped delay line having a plurality of outputs in response to a clock signal;
• (b) producing a signal indicating completion of propagation of the logic state through a predetermined portion of the delay line;
• (c) operating a phase detector having a first input coupled to receive the clock signal and a second input coupled to receive the indicating signal to produce an adjustment signal indicative of whether a phase of the indicating signal is ahead of or behind a phase of the clock signal;
• and
• (d) increasing or decreasing a delay of the delay line in response to the adjustment signal to cause a time required for the logic state to propagate through the predetermined portion of the delay line to be equal to a period of the clock signal,
• wherein the delay line includes a plurality of cascade-connected delay cells each except a first one having an input coupled to an output of another and a plurality of latches each having a set input, a reset input, and an output, the method including steps of coupling a set input of a first latch to an output of a first delay cell to determine a time of occurrence of a leading edge of a timing pulse produced at the output of the first latch, and coupling a reset input of the first latch to an output of a second delay cell to determine a time of occurrence of a trailing edge of a timing pulse produced at the output of the first latch.