FET adaptive limiter with high current FET detector

An FET adaptive limiter for suppressing power spikes, said limiter comprising

• a first attenuating stage having an input terminal for receiving power spikes of input magnitude, a first FET coupled to said input terminal and an output terminal coupled to said first FET for providing power spikes of output magnitude which are diminished in power relative to said input magnitude, said first FET having a gate, a source and a drain, and said first attenuating stage having a first capacitor coupling the source of said first FET to said input terminal of said first stage, a first voltage source directly connected to the drain of said first FET, a second capacitor, a first resistor connected in series with said second capacitor between said drain and the gate of said first FET, a second voltage source, a second FET having a gate coupled to said second voltage source, a source connected directly to the source of said first FET and a drain connected directly to the output terminal of said first attenuating stage, a second resistor coupling said second voltage source to the drain of said second FET and a third resistor coupling said second voltage source to said gate of said first FET;
• and
• a second attenuating stage having an input terminal connected to the output terminal of said first attenuating stage for receiving the power spikes output by said first stage, an additional FET connected to said input terminal of said first attenuating stage and coupled to said input terminal of said second stage and a second stage output terminal coupled to said additional FET for providing power spikes of output magnitude which are considerably diminished in power relative to the input magnitude of said spikes at said input terminal of said first stage.