High performance thin film transistor (TFT) by solid phase epitaxial regrowth
AssigneeMicron Technology, Inc.
InventorsGurtej S. Sandhu, Pierre Fazan
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Abstract
The present invention introduces a method to fabricate an active PMOS thin film transistor (or p-ch TFT) having an epitaxially grown channel region for high performance operation characteristics. Typically this p-ch TFT device would be fabricated overlying an NMOS active device, thereby becoming an active load (or pullup) to an NMOS device used is such applications as creating a memory cell in static random access memories (SRAMs). Conductivity types (p-type or n-type) may be interchanged to construct an n-ch TFT coupled with a PMOS active device if so desired. The fabrication of the TFT of the present invention may be used to form a CMOS inverter or simply an active pullup device when integrated into conventional CMOS fabrication processes.
Claims10
A process for forming an active load in an integrated circuit fabricated on a single crystalline substrate, said process comprising:
- (a) forming a first dielectric layer superjacent existing surface of said single crystalline substrate;
- (b) planarizing said first dielectric layer;
- (c) forming a first semiconductive layer superjacent said planarized first dielectric layer;
- (d) patterning and etching said first semiconductive layer thereby forming a gate terminal to an active device;
- (e) forming dielectric spacers adjacent said patterned edges of said first semiconductive layer;
- (f) forming a second dielectric layer superjacent and coextensive to wafer surface resulting from step "e";
- (g) patterning and etching a buried contact location thereby exposing portions of said single crystalline substrate;
- (h) forming a second semiconductive layer superjacent existing wafer surface resulting from step "g", said second semiconductive layer thereby making physical contact to said exposed portions of single crystalline substrate;
- (i) patterning and etching said second semiconductive material thereby forming a channel region for said active device and
- (j) growing a crystalline structure throughout said patterned second semiconductive material by using said single crystalline substrate as a seed source, said active device serving as said active load.
A process for forming a p-channel thin film transistor in an integrated circuit fabricated on a single crystalline silicon substrate, said process comprising:
- (a) depositing a first oxide layer superjacent existing surface of said single crystalline silicon substrate;
- (b) planarizing said first oxide layer;
- (c) depositing a first polysilicon layer superjacent said planarized first oxide layer;
- (d) patterning and etching said first polysilicon layer thereby forming a gate terminal to said thin film transistor;
- (e) depositing and etching oxide spacers adjacent said patterned edges of said first polysilicon layer;
- (f) forming a second dielectric layer superjacent and coextensive existing substrate surface resulting from step "e";
- (g) patterning and etching a buried contact location thereby exposing portions of said single crystalline silicon substrate;
- (h) depositing a layer of amorphous silicon superjacent existing substrate surface resulting from step "g", said amorphous silicon layer thereby making physical contact to said exposed portions of single crystalline silicon substrate;
- (i) patterning and etching said amorphous silicon layer thereby forming a channel region for said thin film transistor;
- and
- (j) growing epitaxial silicon throughout said patterned amorphous silicon by using said single crystalline silicon substrate as a seed source by annealing existing material on said substrate at a temperature range between 500.degree. to 700.degree. C. for approximately 15 minutes to 6 hours.
Dependencies are inferred from the claim text.