Pipelined apparatus and method for controlled loading of floating point data in a microprocessor

In a microprocessor having a pipelined architecture, said microprocessor comprising a data cache coupled to a floating-point data latch along an internal bus, an apparatus for pipelined accessing of floating-point data from an external memory across an external bus comprising;

• a memory means for accumulating floating-point data;
• a first circuit means for delivering floating-point data from said external memory to said memory means, but not to said data cache, when a cache miss occurs;
• a second circuit means for delivering the floating-point data accumulated in said memory means to said data latch, said second circuit means also coupling said data latch to said first circuit means such that floating-point data resident within said data cache is returned to said memory means in the event of a cache hit;
• and
• a bus control means coupled to said first and second circuit means, said memory means, said internal bus and said data cache for controlling the pipelined flow of floating-point data from said external memory to said data latch without contention of said internal bus by said data cache in the event of a cache miss, and for controlling the return of floating-point data from said data cache to said memory means in the event of a cache hit.

In a processor having a pipelined architecture, a data cache coupled to a floating-point unit along an internal bus, and a bus control unit which controls access to an external memory along an external bus, an apparatus for controlling the pipelined loading of floating-point data into said processor comprising:

• a first buffer coupled to said external bus for receiving floating-point data from said external memory;
• a first circuit means for storing floating-point data in a pipelined manner as it is received from said external memory by said first buffer;
• a first bus coupled to said first circuit means and to said internal bus for transferring the floating-point data stored in said first circuit means to a floating-point data latch in the event of a cache miss;
• a second bus coupling said data cache to said first circuit means such that floating-point data residing in said cache is returned to said first circuit means when a cache hit occurs;
• and
• a control means for controlling said first buffer, said first circuit means, said first, second and internal buses, and said data cache such that floating-point data received from said external bus is not written directly into said data cache, but wherein floating-point data previously stored in said first circuit means is pipelined to said data latch along said first and internal buses without contention of said internal bus by said data cache when a cache miss occurs, floating-point data being returned to said first circuit means from said data cache along said second bus in the event of a cache hit.

In a processor having a floating-point unit, a data cache and a port to an external memory system, a method for pipelined accessing of floating-point data elements from said external memory, said method being executable by instruction means within said processor, said method comprising the steps of:

• (a) issuing an address to a floating-point data element resident within said external memory;
• (b) writing a previously addressed floating-point data element from said external memory to a N-stage, first-in-first-out (FIFO) memory, where N is an integer greater than 1, said FIFO memory storing a Nth previously addressed data element;
• (c) reading said Nth previously addressed floating-point data element from said FIFO memory to a bus;
• (d) transferring said Nth previously addressed floating-point element from said bus to a data latch within said floating-point unit.