US 5,153,880 AGranted

Field-programmable redundancy apparatus for memory arrays

AssigneeXicor, Inc.

InventorsWilliam H. Owen, John Caywood, Joseph Drori, James Jaffe, Isao Nojima, Jeffrey Sung, Ping Wang

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Abstract

A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over the standard signal paths with standard voltage levels of the integrated circuit semiconductor memory array. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundance apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

Claims27

Dependent claims

In an integrated circuit memory array including a plurality of primary memory cells, each said primary memory cell for storing data, a plurality of redundant memory cells, each said redundant memory cell for storing data, address means for enabling each of said primary memory cells to be accessed when a corresponding unique address is coupled thereto on a plurality of address lines, said address means using standard binary logic voltage levels when coupling said unique address onto said address lines, and read/write means for reading data from and for writing data to each said primary memory cell on a plurality of data lines when the address of said primary memory cell is coupled to said address means, said read/write means using standard binary logic voltage levels for data states on said data lines, a field-programmable redundancy system for enabling said integrated circuit memory array to temporarily enter a special reconfiguration mode for replacing a selected one of said primary memory cells with an available one of said plurality of redundant memory cells such that data is exchanged by said read/write means with said redundant memory cell when the address of said replaced primary memory cell is coupled to said address means, comprising:

means for detecting a predetermined code sequence on one or more of said address and data lines;
means for causing said integrated circuit memory array to enter said reconfiguration mode when said predetermined code sequence is detected;
means responsive to said entry into said reconfiguration mode for disabling normal accessing of said primary memory cells by said address means and said read/write means;
means during said reconfiguration mode for receiving the address of a selected primary memory cell to be replaced by a redundant memory cell and for identifying and selecting an available redundant memory cell to be used to replace said selected primary memory cell;
reconfiguration means responsive to said receiving means during said reconfiguration mode for replacing said selected primary memory cell with said selected redundant memory cell such that said selected redundant memory cell is thereafter accessed when the address of said selected primary memory cell is coupled to said address means;
and
means for causing said integrated circuit memory array to exit said reconfiguration mode.

4 more elements

An integrated circuit memory array comprising:

a plurality of primary memory cells, each said primary memory cell for storing data;
a plurality of redundant memory cells, each said redundant memory cell for storing data;
address means for enabling each of said primary memory cells to be accessed when a corresponding unique address is coupled thereto on a plurality of address lines, said address means using standard binary logic voltage levels when coupling said unique address onto said address lines;
read/write means for reading data from and for writing data to each said primary memory cell on a plurality of data lines when the address of said primary memory cell is coupled to said address means, said read/write means using standard binary logic voltage levels for data states on said data lines;
and
means for enabling said integrated circuit memory array to temporarily enter a special reconfiguration mode for replacing a selected one of said primary memory cells with an available one of said plurality of redundant memory cells such that data is exchanged by said read/write means with said redundant memory cell when the address of said replaced primary memory cell is coupled to said address means, said means including:
means for detecting a predetermined code sequence on one or more of said address and data lines;
means for causing said integrated circuit memory array to enter said reconfiguration mode when said predetermined code sequence is detected;
means responsive to said entry into said reconfiguration mode for disabling normal accessing of said primary memory cells by said address means and said read/write means;
means during said reconfiguration mode for receiving the address of a selected primary memory cell to be replaced by a redundant memory cell and for identifying and selecting an available redundant memory cell to be used to replace said selected primary memory cell;
reconfiguration means responsive to said receiving means during said reconfiguration mode for replacing said selected primary memory cell with said selected redundant memory cell such that said selected redundant memory cell is thereafter accessed when the address of said selected primary memory cell is coupled to said address means;
and
means for causing said integrated circuit memory array to exit said reconfiguration mode.

10 more elements

In an integrated circuit memory array including a plurality of primary memory rows, each said primary memory row comprising a plurality of memory bits equal to a predetermined number and for storing data, a plurality of redundant memory rows comprising a plurality of memory bits equal to said predetermined number and for storing data, address means for enabling each of said memory bits of said primary memory rows to be accessed when a corresponding unique address is coupled thereto on a plurality of address lines, said address means using standard binary logic voltage levels when coupling said unique address onto said address lines, said address means arranged such that a predetermined number of said plurality of address lines of said address means are used to address said primary memory rows and are designated as row address lines, and read/write means for reading data from and for writing data to each of said memory bits of said primary memory rows on a plurality of data lines when the address of said primary memory row is coupled to said address means, said read/write means using standard binary logic voltage levels for data states on said data lines, a field programmable redundancy system for enabling said integrated circuit memory array to temporarily enter a special reconfiguration mode for replacing a selected one of said primary memory rows with an available one of said plurality of redundant memory rows such that data is exchanged by said read/write means with said redundant memory row when the row address of said replaced primary memory row is provided to said address means, comprising:

means for detecting a predetermined code sequence on one or more of said address and data lines;
means for causing said integrated circuit memory array to enter said reconfiguration mode when said predetermined code sequence is detected;
means responsive to said entry into said reconfiguration mode for disabling normal access of said primary memory rows by said address means and said read/write means;
means during said reconfiguration mode for receiving the row address of a selected primary memory row to be replaced by a redundant memory row and for identifying and selecting an available redundant memory row to be used to replace said selected primary memory row, said means including a redundancy decoder responsive to signals on one or more of said address lines for selectively addressing each of said redundant memory rows, said redundancy decoder including a plurality of redundant row decoders, each said redundant row decoder responsive to a predetermined address on said address lines for accessing a corresponding one of said redundant memory rows, each said redundant row decoder including a first non-volatile memory for storing the address of a primary memory row, a second non-volatile memory for storing the status of said corresponding redundant memory row as being in use when said redundant memory row is being used as a replacement memory row for one of said primary memory rows, means for detecting a match condition between the primary memory row address appearing on said address lines and the row address stored in said first non-volatile memory and for outputting a match condition signal only when said second non-volatile memory indicates said corresponding redundant memory row is in use, and means responsive to a given primary memory row address appearing on said address lines for outputting a match condition signal on one or more of said data lines when the primary memory row specified by said address has been replaced by one of said redundant memory rows, and for outputting on said data lines the identity of said one of said redundant memory rows replacing said specified primary memory row;
reconfiguration means responsive to said receiving means during said reconfiguration mode for replacing said selected primary memory row with said selected redundant memory row such that said selected redundant memory row is thereafter accessed when the row address of said selected primary memory row is coupled to said address means, said means including means responsive to said match condition signal when said integrated circuit memory array is not in said reconfiguration mode for disabling the addressing of said replaced primary memory row and for enabling the addressing of the redundant memory row corresponding to said redundant row decoder, means for programming each of said first non-volatile memories of said redundant row decoders such that the first non-volatile memory in a selected redundant row decoder is programmed with the row address of the primary memory row to be replaced by the redundant memory row corresponding to said selected redundant row decoder, and means for programming each of said second non-volatile memories of said redundant row decoders to indicate for each said redundant row decoder that its corresponding redundant memory row is in use;
and
means for causing said integrated circuit memory array to exit said reconfiguration mode.

4 more elements

In an integrated circuit memory array having a plurality of primary memory cells and a plurality of redundant memory cells, address lines for selectively addressing each of said primary memory cells and one or more data lines for writing of data to or read out of data from each said primary memory cell when that cell has been selectively addressed, a method for replacing a defective one of said primary memory cells with an available one of said redundant memory cells comprising the steps of:

detecting a first predetermined code sequence on one or more of said address and data lines of said integrated circuit memory array;
causing said integrated circuit memory array to enter a reconfiguration mode of operation when said first predetermined code sequence is detected;
identifying and selecting an available redundant memory cell in said reconfiguration mode;
replacing said defective primary cell with said selected available redundant cell in said reconfiguration mode such that said selected redundant memory cell is accessed for data transfer on said data lines when the address of said defective primary memory cell is thereafter placed on said address lines;
and
causing said integrated circuit memory array to exit said reconfiguration mode of operation when a second predetermined code sequence is detected on one or more of said address and data lines.

3 more elements

Dependencies are inferred from the claim text.