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US 5,151,981 AGranted
Instruction sampling instrumentation
AssigneeInternational Business Machines Corporation
InventorsDouglas W. Westcott, Valerie White
Life of this patent
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AssigneeInternational Business Machines Corporation
InventorsDouglas W. Westcott, Valerie White
Estimating the term…
A system and method for instrumenting the execution of instructions in an out-of-sequence execution machine. Instructions tagged with a preselected instruction identification number (IID) are identified. When an instruction having the preselected IID is encountered, information associated with that instruction is saved as the out-of-sequence execution proceeds. If the instruction completes, the information is stored as a single instrumentation entry in a memory array. If the instruction does not complete, the information is disposed of. The process id repeated for each instruction having the preselected IID until the memory array is full. The storage of instruction information in the memory can be further conditioned on the occurrence of a cache miss or other system conditions.
An apparatus for monitoring execution of instructions in an out-of-sequence execution machine of a type that tags each instruction in an execution pipeline with an instruction identification number, comprising:
An apparatus for monitoring execution of instructions in and out-of sequence execution central processor, comprising:
A method for monitoring execution of instructions in an out-of-sequence execution machine of a type that tags each instruction in an execution pipeline with an instruction identification number, comprising the steps of:
A method for monitoring execution of instructions in an out-of-sequence execution machine of a type in which each instruction in an execution pipeline is tagged with a sequentially assigned instruction identification number, comprising the steps of:
Dependencies are inferred from the claim text.
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Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of…:…
Performance evaluation by tracing or monitoring: circuit details, i.e. tracer hardware
Computing and data processing
Term ended 13 Jul 2010 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
This invention relates to instrumentation and monitoring in digital computers. More specifically, this invention relates to instrumentation and monitoring of processors that can execute instructions in an out-of-sequence fashion.
2. Related Art
FIG. 1 is a block diagram example of out-of-sequence execution.
FIG. 2 is a block diagram of a data processing system containing the invention.
FIG. 3 is a block diagram of an embodiment of the invention in an ITU in any CPU of FIG. 1.
Instruction Sampling provides a system and method for monitoring the processing of instructions in an out-of-sequence execution machine. Each of a sequence of instructions in the execution pipeline of an out-of-sequence execution machine is tagged with an Instruction Identity number (IID). In accordance with the preferred embodiment of instruction sampling, the CPU instrumentation identifies instructions tagged with an IID 24 (hereinafter IID 24 instructions). When an an IID 24 cache hit/miss data and other information of interest instruction is encountered, the Op Code, execution data, associated with that instruction is captured in a plurality of registers distributed throughout the Central Processor (CPU).
As the information of interest is captured, the instrumentation monitors the CPU to determine if the encountered IID 24 instruction has completed execution. If the encountered IID 24 instruction completes and meets user selected trigger conditions, the captured information associated with that instruction is stored in an instrumentation array as a single instrumentation entry. If the encountered IID 24 instruction does not complete, or does not meet the trigger conditions, then the data associated with the next encountered IID 24 instruction is captured in the registers. The above process is repeated for each encountered IID 24 instruction until terminated by the system, instrumentation program, or user.
The application of instruction sampling to CPU instrumentation will be better understood by reference to FIG. 3. During the processing of instructions, machine signals 31 A to Z are generated by an out-of-sequence type CPU. As they are generated, machine signals associated with the execution of each IID 24 instruction are identified and captured (collected) in a signal collector 304. On each sampling pulse generated by the sampling pulse trigger logic 318, the data captured in the signal collector 304 is written as an entry into an instrumentation table array 32 under control of an address generator 33. The data in the instrumentation table array 32 can be selectively output to storage (e.g. magnetic tape 212) via a MUX 316 on command of a processor controller element 206 (FIG. 2).