US 5,151,759 A · Fermi threshold silicon-on-insulator field effect transistor

Abstract

A Silicon-on-Insulator (SOI) field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the thin semiconductor layer in which the transistor is fabricated. The FET, referred to as a Fermi Threshold SOI FET or Fermi SOI FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate channel doping. The vertical electric field in the substrate channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. The thin silicon layer in which the devices are formed is sufficiently thick such that the channel is not fully depleted at pinch-off. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Multiple gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance.

Claims39

Dependent claims

A field effect transistor comprising:

a thin semiconductor layer having a first surface and a second surface opposite said first surface;
source and drain regions of first conductivity type in said thin semiconductor layer;
a channel substrate of second conductivity type, in said thin semiconductor layer at said second surface, between said source and drain regions;
a channel of said first conductivity type in said thin semiconductor layer at said first surface, between said source and drain regions, said channel having a predetermined depth from said first surface;
a gate insulating layer on said thin semiconductor layer at said first surface adjacent said channel, at least one of the source doping, source depth, drain doping, drain depth, channel substrate doping, channel substrate depth, channel doping and channel depth being selected to produce zero static electric field perpendicular to said first surface at said first surface between said channel and said gate insulating layer;
and
source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively.

4 more elements

A field effect transistor comprising:

a thin semiconductor layer having a first surface and a second surface opposite said first surface;
source and drain regions of first conductivity type in said thin semiconductor layer;
a channel substrate of second conductivity type, in said thin semiconductor layer at said second surface, between said source and drain regions;
a channel of said first conductivity type in said thin semiconductor layer at said first surface, between said source and drain regions, said channel having a predetermined depth from said first surface;
a gate insulating layer on said thin semiconductor layer at said first surface adjacent said channel, at least one of the source doping, source depth, drain doping, drain depth, channel substrate doing, channel substrate depth, channel doping and channel depth being selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said channel substrate;
and
source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively.

4 more elements

A field effect transistor comprising:

a thin semiconductor layer having a first surface and a second surface opposite said first surface;
source and drain regions of first conductivity type in said thin semiconductor layer;
a channel substrate of second conductivity type, in said thin semiconductor layer at said second surface, between said source and drain regions;
a channel of said first conductivity type in said thin semiconductor layer at said first surface, between said source and drain regions, said channel having a predetermined depth from said first surface and a predetermined length from said source to said drain;
a gate insulating layer on said thin semiconductor layer at said first surface adjacent said channel and having a predetermined thickness, at least one of the source doping, source depth, drain doping, drain depth, channel substrate doping, channel substrate depth, channel doping and channel depth being selected to produce a threshold voltage for said field effect transistor which is independent of said predetermined length and said predetermined thickness;
and
source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively.

4 more elements

A field effect transistor comprising:

a thin semiconductor layer having a first surface and a second surface opposite said first surface, said thin semiconductor layer having an intrinsic carrier concentration N.sub.i at temperature T degrees Kelvin, and a dielectric constant e.sub.s ;
source and drain regions of first conductivity type in said thin semiconductor layer;
a channel substrate of second conductivity type, in said thin semiconductor layer at said second surface, between said source and drain regions, and being doped at a first dopant density N.sub.a ;
a channel of said first conductivity type in said thin semiconductor layer at said first surface between said source and drain regions, said channel being doped at a second dopant density which is a factor .alpha. times said first dopant density N.sub.a, said channel having a predetermined depth A from said first surface, with A being .sqroot.(2e.sub.s .phi..sub.s)/(qN.sub.a .alpha.(.alpha.+1)), where .phi..sub.s is (2KT/q)ln(N.sub.a /N.sub.i), q is equal to 1.6.times.10.sup.-19 coulombs, and K is equal to 1.3.times.10.sup.-23 Joules/.degree.Kelvin;
a gate insulating layer on said thin semiconductor layer at said first surface adjacent said channel;
and
source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively.

4 more elements

Dependencies are inferred from the claim text.

Fermi threshold silicon-on-insulator field effect transistor

Life of this patent

Fermi threshold silicon-on-insulator field effect transistor

Life of this patent

Abstract

Claims39